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Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard)

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Please see Set 1 for Execution, Stages and Performance (Throughput) and Set 3 for Types of Pipeline and Stalling.   Dependencies in a pipelined processor There are mainly three types of dependencies possible in a pipelined processor. These are : 1) Structural Dependency 2) Control Dependency 3) Data Dependency These dependencies may introduce stalls in the pipeline. Stall : A stall is a cycle in the pipeline without new input.   Structural dependency This dependency arises due to the resource conflict in the pipeline. A resource conflict is a situation when more than one instruction tries to access the same resource in the same cycle. A resource can be a register, memory, or ALU. Example:

Instruction / Cycle 1 2 3 4 5
I1 IF(Mem) ID EX Mem  
I2   IF(Mem) ID EX  
I3     IF(Mem) ID EX
I4       IF(Mem) ID

In the above scenario, in cycle 4, instructions I1 and I4 are trying to access same resource (Memory) which introduces a resource conflict. To avoid this problem, we have to keep the instruction on wait until the required resource (memory in our case) becomes available. This wait will introduce stalls in the pipeline as shown below:

Cycle 1 2 3 4 5 6 7 8
I1 IF(Mem) ID EX Mem WB      
I2   IF(Mem) ID EX Mem WB    
I3     IF(Mem) ID EX Mem WB  
I4       IF(Mem)  

  Solution for structural dependency To minimize structural dependency stalls in the pipeline, we use a hardware mechanism called Renaming. Renaming : According to renaming, we divide the memory into two independent modules used to store the instruction and data separately called Code memory(CM) and Data memory(DM) respectively. CM will contain all the instructions and DM will contain all the operands that are required for the instructions.

Instruction/ Cycle 1 2 3 4 5 6 7
I4       IF(CM) ID EX DM
I5         IF(CM) ID EX
I6           IF(CM) ID
I7             IF(CM)

    Control Dependency (Branch Hazards) This type of dependency occurs during the transfer of control instructions such as BRANCH, CALL, JMP, etc. On many instruction architectures, the processor will not know the target address of these instructions when it needs to insert the new instruction into the pipeline. Due to this, unwanted instructions are fed to the pipeline. Consider the following sequence of instructions in the program: 100: I1 101: I2 (JMP 250) 102: I3 . . 250: BI1 Expected output: I1 -> I2 -> BI1 NOTE: Generally, the target address of the JMP instruction is known after ID stage only.

Instruction/ Cycle 1 2 3 4 5 6
I2   IF ID (PC:250) EX Mem WB
I3     IF ID EX Mem
BI1       IF ID EX

Output Sequence: I1 -> I2 -> I3 -> BI1 So, the output sequence is not equal to the expected output, that means the pipeline is not implemented correctly. To correct the above problem we need to stop the Instruction fetch until we get target address of branch instruction. This can be implemented by introducing delay slot until we get the target address.

Instruction/ Cycle 1 2 3 4 5 6
I2   IF ID (PC:250) EX Mem WB
BI1       IF ID EX

Output Sequence: I1 -> I2 -> Delay (Stall) -> BI1 As the delay slot performs no operation, this output sequence is equal to the expected output sequence. But this slot introduces stall in the pipeline. Solution for Control dependency Branch Prediction is the method through which stalls due to control dependency can be eliminated. In this at 1st stage prediction is done about which branch will be taken.For branch prediction Branch penalty is zero. Branch penalty : The number of stalls introduced during the branch operations in the pipelined processor is known as branch penalty. NOTE : As we see that the target address is available after the ID stage, so the number of stalls introduced in the pipeline is 1. Suppose, the branch target address would have been present after the ALU stage, there would have been 2 stalls. Generally, if the target address is present after the kth stage, then there will be (k – 1) stalls in the pipeline. Total number of stalls introduced in the pipeline due to branch instructions = Branch frequency * Branch Penalty     Data Dependency (Data Hazard) Let us consider an ADD instruction S, such that S : ADD R1, R2, R3 Addresses read by S = I(S) = {R2, R3} Addresses written by S = O(S) = {R1} Now, we say that instruction S2 depends in instruction S1, when pipelining 7 This condition is called Bernstein condition. Three cases exist:

  • Flow (data) dependence/ True Dependence: O(S1) ∩ I (S2), S1 → S2 and S1 writes after something read by S2
  • Anti-dependence: I(S1) ∩ O(S2), S1 → S2 and S1 reads something before S2 overwrites it
  • Output dependence: O(S1) ∩ O(S2), S1 → S2 and both write the same memory location.

Example: Let there be two instructions I1 and I2 such that: I1 : ADD R1, R2, R3 I2 : SUB R4, R1, R2 When the above instructions are executed in a pipelined processor, then data dependency condition will occur, which means that I2 tries to read the data before I1 writes it, therefore, I2 incorrectly gets the old value from I1.

Instruction / Cycle 1 2 3 4
I2   IF ID(Old value) EX

To minimize data dependency stalls in the pipeline, operand forwarding is used. Operand Forwarding : In operand forwarding, we use the interface registers present between the stages to hold intermediate output so that dependent instruction can access new value from the interface register directly. Operand Forwarding can avoid stalls only if the dependent instructions are ALU type instructions. Considering the same example: I1 : ADD R1, R2, R3 I2 : SUB R4, R1, R2

Instruction / Cycle 1 2 3 4

    Data Hazards Data hazards occur when instructions that exhibit data dependence, modify data in different stages of a pipeline. Hazard cause delays in the pipeline. There are mainly three types of data hazards: 1) RAW (Read after Write) [Flow/True data dependency] 2) WAR (Write after Read) [Anti-Data dependency] 3) WAW (Write after Write) [Output data dependency] Let there be two instructions I and J, such that J follow I. Then,

  • Instruction depend on result of prior instruction still in the pipeline.
  • It can occur among the operands in the instruction at the pipeline stages.
  • It occur when instructions read or write registers that are used by other instructions.
  • RAW hazard occurs when instruction J tries to read data before instruction I writes it. Eg: I: R2 <- R1 + R3 J: R4 <- R2 + R3
  • WAR hazard occurs when instruction J tries to write data before instruction I reads it. Eg: I: R2 <- R1 + R3 J: R3 <- R4 + R5
  • WAW hazard occurs when instruction J tries to write output before instruction I writes it. Eg: I: R2 <- R1 + R3 J: R2 <- R4 + R5

WAR and WAW hazards occur during the out-of-order execution of the instructions.   Sources :   This article has been contributed by Saurabh Sharma.   Please write comments if you find anything incorrect, or you want to share more information about the topic discussed above

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Last Updated : 11 Apr, 2023
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