Reduced Set Instruction Set Architecture (RISC) –
The main idea behind is to make hardware simpler by using an instruction set composed of a few basic steps for loading, evaluating and storing operations just like a load command will load data, store command will store the data.
Complex Instruction Set Architecture (CISC) –
The main idea is that a single instruction will do all loading, evaluating and storing operations just like a multiplication command will do stuff like loading data, evaluating and storing it, hence it’s complex.
Both approaches try to increase the CPU performance
- RISC: Reduce the cycles per instruction at the cost of the number of instructions per program.
- CISC: The CISC approach attempts to minimize the number of instructions per program but at the cost of increase in number of cycles per instruction.
Earlier when programming was done using assembly language, a need was felt to make instruction do more task because programming in assembly was tedious and error prone due to which CISC architecture evolved but with up rise of high level language dependency on assembly reduced RISC architecture prevailed.
Characteristic of RISC –
- Simpler instruction, hence simple instruction decoding.
- Instruction come under size of one word.
- Instruction take single clock cycle to get executed.
- More number of general purpose register.
- Simple Addressing Modes.
- Less Data types.
- Pipeline can be achieved.
Characteristic of CISC –
- Complex instruction, hence complex instruction decoding.
- Instruction are larger than one word size.
- Instruction may take more than single clock cycle to get executed.
- Less number of general purpose register as operation get performed in memory itself.
- Complex Addressing Modes.
- More Data types.
Example – Suppose we have to add two 8-bit number:
- CISC approach: There will be a single command or instruction for this like ADD which will perform the task.
- RISC approach: Here programmer will write first load command to load data in registers then it will use suitable operator and then it will store result in desired location.
So, add operation is divided into parts i.e. load, operate, store due to which RISC programs are longer and require more memory to get stored but require less transistors due to less complex command.
|Focus on software||Focus on hardware|
|Uses only Hardwired control unit||Uses both hardwired and micro programmed control unit|
|Transistors are used for more registers||Transistors are used for storing complex
|Fixed sized instructions||Variable sized instructions|
|Can perform only Register to Register Arithmetic operations||Can perform REG to REG or REG to MEM or MEM to MEM|
|Requires more number of registers||Requires less number of registers|
|Code size is large||Code size is small|
|A instruction execute in single clock cycle||Instruction take more than one clock cycle|
|A instruction fit in one word||Instruction are larger than size of one word|
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- Difference between RISC and CISC processor | Set 2
- Differences between Computer Architecture and Computer Organization
- Computer Organization | Basic Computer Instructions
- Computer Organization | Performance of Computer
- Computer Organization and Architecture | Pipelining | Set 1 (Execution, Stages and Throughput)
- Computer Organization and Architecture | Pipelining | Set 3 (Types and Stalling)
- Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard)
- Computer Organization | Amdahl's law and its proof
- Computer Organization | Instruction Formats (Zero, One, Two and Three Address Instruction)
- Computer Organization | Locality and Cache friendly code
- Cache Memory in Computer Organization
- Computer Organization | Hardwired v/s Micro-programmed Control Unit
- Computer Organization | Micro-Operation
- Computer Organization | Different Instruction Cycles
- Computer Organization | Booth's Algorithm
- Computer Organization | Problem Solving on Instruction Format
- Computer Organization | Von Neumann architecture
- Computer Organization | Asynchronous input output synchronization
- Last Minute Notes Computer Organization
- BUS Arbitration in Computer Organization
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