In Synchronous data transfer, the sending and receiving units are enabled with same clock signal. It is possible between two units when each of them knows the behavior of the other. The master performs a sequence of instructions for data transfer in a predefined order. All these actions are synchronized with the common clock. The master is designed to supply the data at a time when the slave is definitely ready for it. Usually, the master will introduce sufficient delay to take into account the slow response of the slave, without any request from the slave.
The master does not expect any acknowledgement signal from the slave, when a data is sent by the master to the slave. Similarly, when a data from the slave is read by the master, neither the slave informs that the data has been placed on the data bus nor the master acknowledges that the data has been read. Both the master and slave performs their own task of transferring data at designed clock period. Since both devices know the behavior (response time) of each other, no difficulty arises.
Prior to transferring data, the master must logically select the slave either by sending slave’s address or sending “device select” signal to the slave. But there are no acknowledgement signal from the slave to master if device is selected.
Timing diagram of synchronous read operation is given below:
In this timing diagram, the master first places slave’s address in the address bus and read signal in the control line at the falling edge of the clock . The entire read operation is over in one clock period.
- The design procedure is easy. The master does not wait for any acknowledges signal from the slave through the master waits for a time equal to slave’s response time.
- The slave does not generate acknowledge signal, though it obeys the timing rules as per the protocol set by the master or system designer.
- If a slow speed unit connected to a common bus, it can degrade overall rate of transfer in the system.
- If the slave operates at a slow speed, the master will be idle for some time during data transfer and vice versa.
- Cache Organization | Set 1 (Introduction)
- Cache Memory in Computer Organization
- Computer Arithmetic | Set - 1
- Computer Arithmetic | Set - 2
- Computer Organization and Architecture | Pipelining | Set 1 (Execution, Stages and Throughput)
- Computer Organization and Architecture | Pipelining | Set 3 (Types and Stalling)
- Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard)
- Computer Organization | Amdahl's law and its proof
- Computer Organization | Hardwired v/s Micro-programmed Control Unit
- MongoDB Python | Insert and Update Data
- Computer Architecture | Flynn's taxonomy
- Clusters In Computer Organisation
- Generations of Computer
- Simplified Instructional Computer (SIC)
- Computer Organization | Micro-Operation
If you like GeeksforGeeks and would like to contribute, you can also write an article using contribute.geeksforgeeks.org or mail your article to email@example.com. See your article appearing on the GeeksforGeeks main page and help other Geeks.
Please Improve this article if you find anything incorrect by clicking on the "Improve Article" button below.