Computer Organization and Architecture

Number of sets in cache = v. So, main memory block j will be mapped to set (j mod v), which will be any one of the cache lines from (j mod v) * k to (j mod v) * k + (k-1). (Associativity plays no role in mapping- k-way associativity means there are k spaces for a block and hence reduces the chances of replacement.)

MBR - Memory Buffer Register ( that stores the data being transferred to and from the immediate access store) MAR - Memory Address Register ( that holds the memory location of data that needs to be accessed.) PC - Program Counter ( It contains the address of the instruction being executed at the current time ) The 1st instruction places the value of PC into MBR The 2nd instruction places an address X into MAR. The 3rd instruction places an address Y into PC. The 4th instruction places the value of MBR ( which was the old PC value) into Memory. Now it can be seen from the 1st and the 4th instructions, that the control flow was not sequential and the value of PC was stored in the memory, so that the control can again come back to the address where it left the execution. This behavior is seen in the case of interrupt handling. And here X can be the address of the location in the memory which contains the beginning address of Interrupt service routine. And Y can be the beginning address of Interrupt service routine. In case of conditional branch (as for option C ) only PC is updated with the target address and there is no need to store the old PC value into the memory. And in the case of Instruction fetch and operand fetch ( as for option A and B), PC value is not stored anywhere else. Hence option D.

Pipeline will have to be stalled till Ei stage of l4 completes, 
as Ei stage will tell whether to take branch or not. 

After that l4(WO) and l9(Fi) can go in parallel and later the
following instructions.
So, till l4(Ei) completes : 7 cycles * (10 + 1 ) ns = 77ns
From l4(WO) or l9(Fi) to l12(WO) : 8 cycles * (10 + 1)ns = 88ns
Total = 77 + 88 = 165 ns

RAM chip size = 1k ×8[1024 words of 8 bits each]
RAM to construct =16k ×16
Number of chips required = (16k x 16)/ ( 1k x 8)
                         = (16 x 2)
[16 chips vertically with each having 2 chips
horizontally]
So to select one chip out of 16 vertical chips, 
we need 4 x 16 decoder.

Available decoder is  2 x 4 decoder
To be constructed is 4 x 16 decoder

Hence 4 + 1 = 5 decoders are required.

r1......r2
a.......b......c = a + b
a.......c......x = c * c
a.......x......but we will have to store c in mem as we don't know if x > a
................. or not
y.......x......y = a * a
choosing the best case of x > a , min spills = 1 

Note that for solving the above problem we are not allowed for code motion. So, we will start analyzing the code line by line and determine how many registers will be required to execute the above code snippet. Assuming the registers are numbered R1, R2, R3 and R4. The analysis has been shown in the table below So from the above analysis we can conclude that we will need minimum 4 registers to execute the above code snippet. This explanation has been contributed by Namita Singh.

For a 4 bit multiplier, there are 2⁴ * 2⁴ combinations, i.e., 2⁸ combinations. Also, Output of a 4 bit multiplier is 8 bits. Thus, the amount of ROM needed = 2⁸ * 8 = 2¹¹ = 2048 bits = 2Kbits

Register renaming is done to avoid WAR and WAW data hazards.

A set-associative scheme is a hybrid between a fully associative cache, and direct mapped cache. It's considered a reasonable compromise between the complex hardware needed for fully associative caches (which requires parallel searches of all slots), and the simplistic direct-mapped scheme, which may cause collisions of addresses to the same slot (similar to collisions in a hash table). (source: http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Memory/set.html). Also see http://csillustrated.berkeley.edu/PDFs/handouts/cache-3-associativity-handout.pdf   Number of blocks = Cache-Size/Block-Size = 256 KB / 32 Bytes = 2¹³ Number of Sets = 2¹³ / 4 = 2¹¹ Tag + Set offset + Byte offset = 32 Tag + 11 + 5 = 32 Tag = 16

16 bit address 2 bit valid 1 modified 1 replace Total bits = 20 20 × no. of blocks = 160 K bits.