Prerequisite – Addressing Modes
Addressing modes are the operations field specifies the operations which need to be performed. The operation must be executed on some data which is already stored in computer registers or in the memory. The way of choosing operands during program execution is dependent on addressing modes of the instruction. “The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually referenced. “Basically how we are interpreting the operand which is given in the instruction is known as addressing mode.
Addressing mode very much depend on the type of CPU organisation. There are three types of CPU organisation:
- Single Accumulator organisation
- General register organisation
- Stack organisation
Addressing modes is used for one or both of the purpose. These can also be said as the advantages of using addressing mode:
- To give programming versatility to the user by providing such facilities as pointers to memory, counter for loop control, indexing of data, and program relocation.
- To reduce the number of bits in the addressing field of the instruction.
There are numbers of addressing modes available and it depends on the architecture and CPU organisation which of the addressing modes can be applied.
|Memory Based Addressing Modes||Register Based Addressing Modes|
|The operand is present in memory and its address is given in the instruction itself. This addressing mode is taking proper advantage of memory address, e.g., Direct addressing mode||An operand will be given in one of the register and register number will be provided in the instruction.With the register number present in instruction, operand is fetched, e.g., Register mode|
|The memory address specified in instruction may give the address where the effective address is stored in the memory. In this case effective memory address is present in the memory address which is specified in the instruction, e.g., Indirect Addressing Mode||The register contains the address of the operand. The effective address can be derived from the content of the register specified in the instruction. The content of the register might not be the effective address. This mode takes full advantage of registers, e.g., Register indirect mode|
|The content of base register is added to the address part of the instruction to obtain the effective address. A base register is assumed to hold a base address and the address field of the instruction gives displacement relative to the base address, e.g., Base Register Addressing Mode||If we are having a table of data and our program needs to access all the values one by one we need something which decrements the program counter/or any register which has base address. Though in this case register is basically decreased, it is register based addressing mode, e.g., In Auto decrements mode|
|The content of the index register is added to the address part that is given in the instruction to obtain the effective address. Index Mode is used to access an array whose elements are in successive memory locations, e.g., Indexed Addressing Mode||If we are having a table of data and our program needs to access all the values one by one we need something which increment the program counter/or any register which has base address, e.g., Auto increment mode|
|The content of program counter is added to the address part of the instruction in order to obtain the effective address. The address part of the instruction in this case is usually a signed number which can be either positive or negative, e.g., Relative addressing mode||Instructions generally used for initializing registers to a constant value is register based addressing mode,and this technique is very useful approach, e.g., Immediate mode.|
Memory based addressing modes are mostly rely on Memory address and content present at some memory location. Register based addressing modes are mostly rely on Registers and content present at some register either it is data or some memory address.
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- Computer Organization | General Register based CPU Organization
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