Suppose any device which is connected at input-output port wants to transfer data to transfer data to memory, first of all it will send input-output port address and control signal, input-output read to input-output port, then it will send memory address and memory write signal to memory where data has to be transferred. In normal input-output technique the processor becomes busy in checking whether any input-output operation is completed or not for next input-output operation, therefore this technique is slow.
This problem of slow data transfer between input-output port and memory or between two memory is avoided by implementing Direct Memory Access (DMA) technique. This is faster as the microprocessor/computer is bypassed and the control of address bus and data bus is given to the DMA controller.
- HOLD – hold signal
- HLDA – hold acknowledgment
- DREQ – DMA request
- DACK – DMA acknowledgment
Suppose a floppy drive which is connected at input-output port wants to transfer data to memory, the following steps are performed:
- Step-1: First of all the floppy drive will send DMA request (DREQ) to the DMAC, it means the floppy drive wants its DMA service.
- Step-2: Now the DMAC will send HOLD signal to the CPU.
- Step-3: After accepting the DMA service request from the DMAC, the CPU will send hold acknowledgement (HLDA) to the DMAC, it means the microprocessor has released control of the address bus the data bus to DMAC and the microprocessor/computer is bypassed during DMA service.
- Step-4: Now the DMAC will send one acknowledgement (DACL) to the floppy drive e=which is connected at the input-output port. It means the DMAC tells the floppy drive be ready for its DMA service.
- Step-5: Now with the help of input-output read and memory write signal the data is transferred from the floppy drive to the memory.
Modes of DMAC:
- Single Mode – In this only one channel is used, means only a single DMAC is connected to the bus system.
- Cascade Mode – In this multiple channels are used, we can further cascade more number of DMACs.
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