Cache is close to CPU and faster than main memory. But at the same time is smaller than main memory. The cache organization is about mapping data in memory to a location in cache.
A Simple Solution:
One way to go about this mapping is to consider last few bits of long memory address to find small cache address, and place them at the found address.
Problems With Simple Solution:
The problem with this approach is, we loose the information about high order bits and have no way to find out the lower order bits belong to which higher order bits.
What is a Cache Block?
Since programs have Spatial Locality (Once a location is retrieved, it is highly probable that the nearby locations would be retrieved in near future). So a cache is organized in the form of blocks. Typical cache block sizes are 32 bytes or 64 bytes.
The above arrangement is Direct Mapped Cache and it has following problem
We have discussed above that last few bits of memory addresses are being used to address in cache and remaining bits are stored as tag. Now imagine that cache is very small and addresses of 2 bits. Suppose we use the last two bits of main memory address to decide the cache (as shown in below diagram). So if a program accesses 2, 6, 2, 6, 2, …, every access would cause a hit as 2 and 6 have to be stored in same location in cache.
Solution to above problem – Associativity
What if we could store data at any place in cache, the above problem won’t be there? That would slow down cache, so we do something in between.
We will soon be discussing more details of cache organization.
This article is contributed Ankur Gupta. Please write comments if you find anything incorrect, or you want to share more information about the topic discussed above
Attention reader! Don’t stop learning now. Get hold of all the important CS Theory concepts for SDE interviews with the CS Theory Course at a student-friendly price and become industry ready.
- Locality of Reference and Cache Operation in Cache Memory
- Cache Memory in Computer Organization
- Computer Organization | Locality and Cache friendly code
- Cache Hits in Memory Organization
- Introduction of Stack based CPU Organization
- Introduction of Single Accumulator based CPU organization
- Introduction of General Register based CPU Organization
- What's difference between CPU Cache and TLB?
- Multilevel Cache Organisation
- Cache Coherence Protocols in Multiprocessor System
- Difference between Virtual memory and Cache memory
- Cache Memory Design
- Write Through and Write Back in Cache
- Types of Cache Misses
- Differences between Associative and Cache Memory
- Concept of Cache Memory Design
- Cache Coherence
- Difference between RAM and Cache
- Difference between Buffer and Cache
- Difference between Cache Memory and Register