GATE | SCHOLARSHIP | Question 2

Assume a computer has on-chip and off-chip caches, main memory and virtual memory. Assume the following hit rates and access times: on-chip cache 95%, 1 ns, off-chip cache 99%, 10 ns, main memory: X%, 50 ns, virtual memory: 100%, 2,500,000 ns. Notice that the on-chip access time is 1 ns. We do now want our effective access time to increase much beyond 1 ns. Assume that an acceptance effective access time is 1.6 ns. What should X be (the hit rate of memory) to ensure that EAT is no worse than 1.6 ns?

(A)

90%

(B)

85%

(C)

99.99%

(D)

95%

Answer: (C)

Explanation:

EAT = 1ns + .05 * (10 ns + .01 * (50 ns + (1 – X) * 2,500,000 ns)).
Since we want EAT to be no more than 1.6 ns, we solve for X with
1.6 ns = 1ns + .05 * (10 ns + .01 * (50 ns + (1 – X) * 2,500,000 ns)).
X = 1 – ((((((1.25 ns – 1 ns) / .05) – 10 ns) / .01) – 50 ns) / 2,500,000).
X = 0.99994 = 99.994%.
Our miss rate for virtual memory must be no worse than .006%!

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