A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c − byte chunks are mapped on consecutive banks with wrap-around. All the k banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may
involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes. k/2 ns The latency of one bank access is 80 ns. If c = 2 and k = 24, the latency of retrieving a cache block starting at address zero from main memory is:
(A) 92 ns
(B) 104 ns
(C) 172 ns
(D) 184 ns


Answer: (D)

Explanation: Explanation:

Size of cache block=64 B
No. of main memory banks K=24
Size of each bank C=2 bytes
i.e each bank in memory is 2 bytes and there are 24 such banks. So, in one iteration we can get 2*24 = 48 bytes and getting 64 bytes requires 2 iterations.
So time taken for  parallel access T=decoding time +latency time.
T = (K/2)+latency
= 12+80 = 92 ns
But C=2 for accesses
=2*92=184ns
(since in each iteration we need to select the banks and the bank decoding time (k/2) is independent of the number of banks we are going to access)

This solution is contributed by Nitika Bansal.

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