# GATE-CS-2006

Question 1 |

^{2}+ a3x

^{3}, where ai ≠ 0 ∀i. The minimum number of multiplications needed to evaluate p on an input x is:

3 | |

4 | |

6 | |

9 |

**Numerical Methods and Calculus**

**GATE-CS-2006**

**Discuss it**

**Background Explanation :**Horner's rule for polynomial division is an algorithm used to simplify the process of evaluating a polynomial f(x) at a certain value x = x0 by dividing the polynomial into monomials (polynomials of the 1st degree). Each monomial involves a maximum of one multiplication and one addition processes. The result obtained from one monomial is added to the result obtained from the next monomial and so forth in an accumulative addition fashion. To explain the above, let is re-write the polynomial in its expanded form; f(x0) = a0 + a1x0+ a2x0^2+ ... + anx0^n This can, also, be written as: f(x0) = a0 + x0(a1+ x0(a2+ x0(a3+ ... + (an-1 + anx0)....) The algorithm proposed by this rule is based on evaluating the monomials formed above starting from the one in the inner-most parenthesis and move out to evaluate the monomials in the outer parenthesis.

**Solution :**Using Horner's Rule, we can write the polynomial as following a0 + (a1 + (a2 + a3x)x)x In the above form, we need to do only 3 multiplications

p = a3 X x ------------ (1) q = (a2 + p) X x ---------(2) r = (a1 + q) X x ---------(3) result = a0 + rReference : http://www.geeksforgeeks.org/horners-method-polynomial-evaluation/ This solution is contributed by

**Nitika Bansal.**

Question 2 |

z ^{2xy} | |

z x 2 ^{xy} | |

z ^{2x + y} | |

2 ^{xyz} |

**Set Theory & Algebra**

**GATE-CS-2006**

**Discuss it**

So number of functions from Z to E =

**(D)**is correct. Source: http://www.cse.iitd.ac.in/~mittal/gate/gate_math_2006.html

Question 3 |

It is not closed | |

2 does not have an inverse | |

3 does not have an inverse | |

8 does not have an inverse |

**Set Theory & Algebra**

**GATE-CS-2006**

**Discuss it**

Question 4 |

Neither a Partial Order nor an Equivalence Relation | |

A Partial Order but not a Total Order | |

A Total Order | |

An Equivalence Relation |

**Set Theory & Algebra**

**GATE-CS-2006**

**Discuss it**

**(A)**Neither a Partial Order nor an Equivalence Relation

**(B)**A Partial Order but not a Total Order

**(C)**A Total Order

**(D)**An Equivalence Relation

**Solution:**

An **equivalence relation** on a set x is a subset of x*x, i.e., a collection R of ordered pairs of elements of x, satisfying certain properties. Write “x R y" to mean (x,y) is an element of R, and we say "x is related to y," then the properties are
1. Reflexive: a R a for all a Є R,
2. Symmetric: a R b implies that b R a for all a,b Є R
3. Transitive: a R b and b R c imply a R c for all a,b,c Є R.

An **partial order**** relation** on a set x is a subset of x*x, i.e., a collection R of ordered pairs of elements of x, satisfying certain properties. Write “x R y" to mean (x,y) is an element of R, and we say "x is related to y," then the properties are

1. Reflexive: a R a for all a Є R, 2. Anti-Symmetric: a R b and b R a implies that for all a,b Є R 3. Transitive: a R b and b R c imply a R c for all a,b,c Є R.

An **total order**** relation** a set x is a subset of x*x, i.e., a collection R of ordered pairs of elements of x, satisfying certain properties. Write “x R y" to mean (x,y) is an element of R, and we say "x is related to y," then the properties are

1. Reflexive: a R a for all a Є R, 2. Symmetric: a R b implies that b R a for all a,b Є R 3. Transitive: a R b and b R c imply a R c for all a,b,c Є R. 4. Comparability : either a R b or b R a for all a,b Є R.

As given in question, a relation R is defined on ordered pairs of integers as follows: (x,y) R(u,v) if x < u and y > v , reflexive property is not satisfied here , because there is > or < relationship between (x ,y) pair set and (u,v) pair set . Other way , if there would have been x <= u and y>= v (or x=u and y=v) kind of relation amongs elements of sets then reflexive property could have been satisfied. Since reflexive property in not satisfied here , so given realtion can not be **equivalence ,****partial order**** ****or t****otal order ****relation.**So ,Answer (A) is true** .**

This solution is contributed by **N****irmal Bharadwaj.**

Question 5 |

Ensure packets reach destination within that time | |

Discard packets that reach later than that time | |

Prevent packets from looping indefinitely | |

Limit the time for which a packet gets queued in intermediate routers. |

**Network Layer**

**GATE-CS-2006**

**Discuss it**

Question 6 |

1 | |

2 | |

3 | |

4 |

**GATE-CS-2006**

**OS CPU Scheduling**

**Discuss it**

**Solution:**Let three process be P0, P1 and P2 with arrival times 0, 2 and 6 respectively and CPU burst times 10, 20 and 30 respectively. At time 0, P0 is the only available process so it runs. At time 2, P1 arrives, but P0 has the shortest remaining time, so it continues. At time 6, P2 also arrives, but P0 still has the shortest remaining time, so it continues. At time 10, P1 is scheduled as it is the shortest remaining time process. At time 30, P2 is scheduled. Only two context switches are needed. P0 to P1 and P1 to P2. See question 1 of http://www.geeksforgeeks.org/operating-systems-set-14/ This solution is contributed by

**Nitika Bansal**

Question 7 |

S -> S * E S -> E E -> F + E E -> F F -> idConsider the following LR(0) items corresponding to the grammar above.

(i) S -> S * .E (ii) E -> F. + E (iii) E -> F + .EGiven the items above, which two of them will appear in the same set in the canonical sets-of-items for the grammar?

(i) and (ii) | |

(ii) and (iii) | |

(i) and (iii) | |

None of the above |

**Parsing and Syntax directed translation**

**GATE-CS-2006**

**Discuss it**

Question 8 |

A | |

B | |

C | |

D |

**Digital Logic & Number representation**

**GATE-CS-2006**

**Discuss it**

In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’. Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output. So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

Therefore, (C) is the correct answer.

Please comment below if you find anything wrong in the above post.

Question 9 |

400 | |

500 | |

600 | |

700 |

**Computer Organization and Architecture**

**GATE-CS-2006**

**Discuss it**

Here, size of instruction = 24/8 = 3 bytes. Program Counter can shift 3 bytes at a time to jump to next instruction. So the given options must be divisible by 3. only 600 is satisfied.

Question 10 |

O(n) | |

O(Logn) | |

O(LogLogn) | |

O(1) |

**GATE-CS-2006**

**Discuss it**