Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 100 instructions I1, I2, I3, …, I100 is executed in this pipelined processor. Instruction I17 is the only branch instruction and its branch target is I91. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .
(A) 612
(B) 1854
(C) 1133
(D) 578


Answer: (A)

Explanation:

Instruction          N-th cycle to complete instruction
I1                              5
I2                              6
--                              --
I17                             21
I91                             25      
I92                             26
--                              --
I100                            34

Therefore, total 34 cycles required to complete given program and each instructions required (17+1 =) 18 ns.
So, total time 34*18 = 612 ns needed.

Option (A) is correct.

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