What is JK Flip-Flop ?

In Digital Electronics and communication science, flip-flops are widely used for handling binary information. These fundamental building blocks are used to store and manipulate information as per our needs. From the Flipflop family, Jack Kilby flip-flop(JK Flipflop) is very prominent as it is very versatile and can be used as a basic memory element. It can store binary information, and toggle functionality with a diversity of making applications with it. This article will cover all about JK flipflop.

What is JK Flip-Flop?

It is one kind of sequential logic circuit which stores binary information in bitwise manner. It consists of two inputs and two outputs. Inputs are Set(J) & Reset(K) and their corresponding outputs are Q and Q’. JK flipflop has two modes of operation which are synchronous mode and asynchronous mode. In synchronous mode, the state will be changed with the clock(clk) signal, and in asynchronous mode, the change of state is independent from its clock signal. Let’s see its diagram structure.

The JK flip flop diagram above represents the basic structure which consists of Clock (CLK), Clear (CLR), and Preset (PR).

Below is the circuit diagram of JK Flip Flop. Two 3-input NAND gates are used in place of the original two 2-input AND gates. The outputs at Q and Q’ are coupled to each gate’s third input. Since the two inputs are now interlocked, the SR flip-flop’s cross-coupling enables the previously invalid condition of (S = “1”, R = “1”) to be employed to perform the “toggle action”.

In a circuit “set”, the bottom NAND gate interrupts the J input coming from the “0” position of Q’. In the “RESET” state, the top NAND gate interrupts the K input coming from the 0 positions of Q. We can use Q and Q’ to control the input because they are always different. The flip flop is toggled according to the truth table when both inputs “J” and “K” are set to 1.

Truth Table

JK Flip Flop Truth Table

Applications of JK Flip-Flop

We can simply implement a JK-flipflop using NAND gates. In that case two NAND gates need to be connected together and the output of that will be feed to the input which will create a stable state-holding circuit. The resulting circuit will be the NAND gate. So, by following this mechanism we can develop and use JK-flipflop for various application which are listed below.

• Counters: These are very essential components for the application of frequency dividers and event sequencers where there is a need of storing and propagating the count value. We can design binary synchronous and asynchronous counters using JK-flipflop.
• Shift registers: For data storage and manipulation, serial-to-parallel or parallel-to-serial data conversion the shift registers are widely used. Registers can store and shift the binary data in a sequential manner. We can design it by JK-flipflops.
• Memory Units: JK-flipflop itself act as a memory unit to store binary information. By making a sequential chain of JK-flipflops we can use it even as RAM.

Advantages of JK Flip-Flop

• Versatility: As discussed above, JK-flipflops can be used as a basic memory element or a primary building block of further complex memory design. It is very much adaptive as it can be operated in both synchronous and asynchronous modes.
• Toggle Functionality: The application which are required to get output as its complement of input that also can be developed by JK-flipflops as when J=K=1 it triggers toggle state which gives output which is complement with it’s each clock pulse.
• Error Detection and Correction: We can use a complex circuit built by JK-flipflops which can detect and correct information during data-transmission.

Disadvantages of JK Flip-Flop

• Complexity: Compared to other types of flipflops(D,T, SR), JK flipflop requires additional logic gates to implement which consumes extra memory resources and increases complexity to operate.
• Propagation Delay: This is the major problem present in JK-FF. Propagation delay results a timing delay in certain application which are time-flow sensitive.
• Race Problem: This issue arises when the clock input’s timing pulse isn’t given enough time to turn “Off” before the output Q’s state is altered.