# VHDL code for AND and OR Logic Gates

Prerequisite – Introduction of Logic Gates

Design and implement the **AND** and **OR** logic gates using VHDL (VHSIC Hardware Description Language) programming language.

**1. Logic Development for AND Gate :**

The AND logic gate can be realized as follows –

The truth table for AND Gate is:

A | B | Y = A AND B |
---|---|---|

0 | 0 | 0 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 1 |

**Implementation –**

Below is the implementation of the above logic in VHDL language.

--VHDL Code for AND gate--Header file declarationlibraryIEEE;useIEEE.std_logic_1164.all; --Entity declarationentityandGateisport(A : in std_logic; --AND gate inputB : in std_logic; --AND gate inputY : out std_logic); --AND gate outputendandGate; --Architecture definitionarchitectureandLogicofandGateisbeginY <= A AND B;endandLogic;

**2. Logic Development for OR Gate :**

The OR logic gate can be realized as follows –

The truth table for OR Gate is:

A | B | Y = A OR B |
---|---|---|

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 1 |

**Implementation –**

Below is the implementation of the above logic in VHDL language.

--VHDL Code for OR gate--Header file declarationlibraryIEEE;useIEEE.std_logic_1164.all; --Entity declarationentityorGateisport(A : in std_logic; --OR gate inputB : in std_logic; --OR gate inputY : out std_logic); --OR gate outputendorGate; --Architecture definitionarchitectureorLogicoforGateisbeginY <= A OR B;endorLogic;

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