Prerequisite – Introduction of Logic Gates
Design and implement the AND and OR logic gates using VHDL (VHSIC Hardware Description Language) programming language.
1. Logic Development for AND Gate :
The AND logic gate can be realized as follows –
The truth table for AND Gate is:
A | B | Y = A AND B |
---|---|---|
0 | 0 | 0 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
Implementation –
Below is the implementation of the above logic in VHDL language.
-- VHDL Code for AND gate -- Header file declaration library IEEE; use IEEE.std_logic_1164.all; -- Entity declaration entity andGate is port(A : in std_logic; -- AND gate input B : in std_logic; -- AND gate input Y : out std_logic); -- AND gate output end andGate; -- Architecture definition architecture andLogic of andGate is begin Y <= A AND B; end andLogic;
2. Logic Development for OR Gate :
The OR logic gate can be realized as follows –
The truth table for OR Gate is:
A | B | Y = A OR B |
---|---|---|
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 1 |
Implementation –
Below is the implementation of the above logic in VHDL language.
-- VHDL Code for OR gate -- Header file declaration library IEEE; use IEEE.std_logic_1164.all; -- Entity declaration entity orGate is port(A : in std_logic; -- OR gate input B : in std_logic; -- OR gate input Y : out std_logic); -- OR gate output end orGate; -- Architecture definition architecture orLogic of orGate is begin Y <= A OR B; end orLogic;
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