Parallel Arbitration Logic In Multiprocessors

In multiprocessor systems, the arbitration logic is used to make sure that at a single point in time, only one processor can access the system bus. In this article, we are going to see how the functioning of parallel arbitration logic in multiprocessors takes place.

What is Parallel Arbitration Logic?

Parallel Arbitration Logic provides a mechanism through which the shared resources can be accessed by the processors in a multiprocessor system in a controlled and efficient way. Unlike the sequential arbitration logic, where the processors can access the resources one by one on a priority basis, In parallel arbitration logic these resources can be accessed by the processors simultaneously.

Terminology Used in Parallel Arbitration

Before understanding the working of parallel arbitration logic, let’s take a look at some of the important terminologies:

• Bus Arbiter: In a multiprocessor system, the bus arbiter is a device that is used to decide which processor will be allowed to access the system bus.
• Priority Encoder: It is a device in which the input lines are in the form of 2ⁿ and the output lines generated are in the form of n and the output generated is dependent upon the input with the highest priority.
• Decoder: It is a device in which the input lines are in the form of n and the output lines generated are in the form of 2ⁿ.
• System Bus: It is the path of communication through which the processors in the multiprocessor system can access the resources.
• Bus Request Output Line(Req): Whenever a bus arbiter wants to access the system bus, then in that case it enables the bus request output line for requesting the access.
• Acknowledgment Input Line(Ack): This is a type of signal that is enabled in order to confirm that a processor has been granted access to the resource.

Working

In the parallel bus arbitration technique, the external priority encoder and a decoder are used as shown in the figure given below. Here each bus arbiter is in the parallel scheme with a bus request output line (Req) and a bus acknowledge input line (Ack).

Parallel Arbitration Logic Diagram

Now, Let’s understand the working step by step:

Step 1: Whenever the processor needs to access the system bus, at that moment, the arbiter of that processor enables the request line. ( Suppose, processor 1 wants to access the system bus, then at that time, the bus arbiter 1 will request the priority encoder to give access to the system bus).

Step 2: We can see in the above figure that the requests from the four arbiters are going into a 4×2 priority encoder.

Step 3: And the output generated from the encoder is a 2-bit code which acts as an input for the 2×4 decoder and then the decoder enables the appropriate acknowledgement input line (Ack) so that the highest priority unit can access the system bus.

Step 4: Now the unit which has accessed the system bus can use it for performing its tasks and once the tasks get performed, it releases the bus so that the other processors can access it.

• When the bus is busy conducting a transfer, then the bus busy signal BUSY, which is an open-collector output is used to instruct all the other arbiters that the bus is busy right now and once the bus becomes free, it releases the bus busy line.
• There’s one open-collector output called common bus request (CBRQ), which is used to instruct the arbiter, if there are any other arbiters with lower priority trying to request the bus.
• Corresponding to the request (Req) and acknowledgment (Ack) signals shown in the figure, there are bus request (BREQ) and priority-in (BPRN) signals, which are used to construct a parallel arbitration procedure in which the BREQ signal represents the individual processor which wants to access the bus and the BPRN signal represents that which processor will get the access of the shared resource. And the bus clock (BCLK) is used to synchronize all the bus transactions.

Conclusion

We can conclude that the parallel arbitration logic which works by using some of the key components like priority encoder and decoder is an efficient and controlled way for processors in a multiprocessor system because the processors can request access to the shared resources simultaneously.

Frequently Asked Questions

Q.1: What is the advantage of Parallel Arbitration Logic?

Answer:

The main advantage of the parallel arbitration logic is that it provides a way for processors through which they can request access to the shared resources simultaneously.

Q.2: When does the request line get enabled?

Answer:

The request line gets enabled by the processor whenever it wants to access the system bus to perform some specific tasks using the shared resources.

Q.3: What is the role of the priority encoder and decoder in parallel arbitration?

Answer:

The priority encoder generates a code based on the priority of the input lines which is then decoded by the decoder to enable the appropriate acknowledgement signal(Ack) so that the highest priority unit can access the system bus to perform its tasks.

Q.4: What is a System Bus?

Answer:

It is the path of communication through which the processors in the multiprocessor system can access the required resources.

Q.5: What is the use of a bus busy signal BUSY?

Answer:

Whenever the system bus is busy (accessed by some processor), then at that point in time, the bus busy signal is used to inform all the other arbiters that the bus is busy right now, and once the bus becomes free, it releases the bus busy line.