VAX Architecture was designed to increase the compatibility by improving the hardware of the earlier designed machines. As VAX architecture is an example of the CISC (Complex Instruction Set Computers) therefore there are large and complicated instruction sets used in the system.
VAX architecture consists of 8- bit bytes memory. Two consecutive bytes form a word, four bytes form a longword, eight bytes form a quadword, sixteen bytes form an octaword. All VAX programs operates on Virtual Address Space (232 bytes).
Virtual Address Space is divided into two spaces:
- System Space
- Process Space
VAX architecture have 16 general-purpose registers from R0 to R15. Some of these registers have special name and use.
AP - Argument Pointer FP - Frame Pointer SP - Stack Pointer PC - Program Counter
- Data Formats:
- Integers are stored as Binary numbers in byte, word, longword, quadword or octword.
- Characters are represented using 8-bit ASCII codes.
- Floating points are represented using four different floating-point formats of length ranging from 4 to 16 bytes.
- Instruction Formats:
VAX machine architecture use a variable-length instruction format. Each instruction consists of an operand code (1 or 2 bytes) followed by up to six operand specifier, depending on the type of instruction.
- Addressing Modes:
VAX architecture use a large number of addressing modes. There are number of modes available such as register mode, register deferred mode, autoincrement and autodecrement mode. There are also base relative addressing modes, with displacement fields of different lengths. Program counter relative mode is also used to deal with PC register.
- Instruction Set:
In VAX systems instruction mnemonics are formed by combining following elements:
- Prefix: A Prefix specifies the type of operation.
- Suffix: A Suffix specifies the data type of the operands.
- Modifier: A modifier specifies the number of operand involved.
- Input and Output:
I/O device controller are used to implement I/O on VAX architecture. Each controller has a set of control/status. The portion of the space into which the device controller register are mapped is called I/O space.
- Computer Organization and Architecture | Pipelining | Set 1 (Execution, Stages and Throughput)
- Computer Organization and Architecture | Pipelining | Set 3 (Types and Stalling)
- Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard)
- Hardware architecture (parallel computing)
- Computer Architecture | Flynn's taxonomy
- Computer Organization | Von Neumann architecture
- Differences between Computer Architecture and Computer Organization
- Microarchitecture and Instruction Set Architecture
- Architecture of 8086
- UltraSPARC Architecture
- SIC/XE Architecture
- PowerPC Architecture
- Cray T3E Architecture
- Pentium Pro Architecture
If you like GeeksforGeeks and would like to contribute, you can also write an article using contribute.geeksforgeeks.org or mail your article to firstname.lastname@example.org. See your article appearing on the GeeksforGeeks main page and help other Geeks.
Please Improve this article if you find anything incorrect by clicking on the "Improve Article" button below.