UltraSPARC Architecture belongs to the SPARC (Scalable Processor Architecture) family of processors. This architecture is suitable for wide range of microcomputers and supercomputers. UltraSPARC is example of RISC (Reduced Instruction Set Computer).
Memory consists of 8 bit-bytes. Two consecutive bytes form a halfword, four bytes form a word, eight bytes form a doubleword. UltraSPARC programs operates on Virtual Address Space (264 bytes). Virtual Address Space is divided into pages and these pages are stored in the physical memory or on disk.
UltraSPARC architecture include a large file of registers that have more than 100 general purpose registers. Any procedure can access only 32 registers only. The SPARC hardware uses window into registers file to manage all the operations of different procedures.
Beside these register files, UltraSPARC also uses Program Counter, code register, and other control registers.
- Data Formats:
- Integers are stored as 8-, 16-, 32-, or 64-bit Binary numbers.
- Characters are represented using 8-bit ASCII codes.
- Floating points are represented using three different formats namely single-percision format, double-percision format, quad-percision format.
- Instruction Formats:
SPARC architecture use three basic instruction formats. All the instructions are of 32-bit long and first two bits are used to identify which format is being used.
Format 1- Used for Call instruction.
Format 2- Used for branch instructions.
Format 3- Used by all the remaining instructions like register load and store.
n=Indirect mode, i=Immediate addressing, x=Index addressing, b=Base addressing, p= Program counter, e=Exponential addressing
- Addressing Modes:
Operands in memory are addressed using one of the following three modes:
Mode Target address(TA) calculation PC-relative TA=(PC) + displacement Register indirect TA=(register) + displacement with displacement Register indirect TA=(register-1) + (register-2) indexed
PC-relative is used only for branch instructions.
- Instruction Set:
This architecture have less number of instructions as compared to CISC machines. The only instructins that access memory are load and stores. All other instructions operates on register only. Instruction execution on a SPARC system is pipelined which means while one instruction is executed next one is being fetched from memory and decoded.
- Input and Output:
Communication between I/O devices and SPARC operation are accomplished through memory. Input and Output can be performed with the regular instruction set of the computer, and no special I/O instructions are needed.
- SIC/XE Architecture
- VAX Architecture
- Pentium Pro Architecture
- Cray T3E Architecture
- Architecture of 8086
- PowerPC Architecture
- Microarchitecture and Instruction Set Architecture
- Hardware architecture (parallel computing)
- Computer Organization | Von Neumann architecture
- Computer Architecture | Flynn's taxonomy
- Computer Organization and Architecture | Pipelining | Set 3 (Types and Stalling)
- Computer Organization and Architecture | Pipelining | Set 1 (Execution, Stages and Throughput)
- Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard)
- Difference between Fine-Grained and Coarse-Grained SIMD Architecture
- Differences between Computer Architecture and Computer Organization
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