# Cisco Interview | Set 2

I recently got interviewed for a position in Cisco. The organization came to our college as part of their University recruitment program. The following is my interview experience. Hope this would help you !! Round 1 This was aptitude + technical round. 20 question from aptitude and 30 questions technical. We were given 60 minutes to solve the question. NO NEGATIVE MARKING. The aptitude question were relatively easy. There was a cat and tunnel problem. A question on Venn diagrams was calculation based, 4 different event on Venn diagram. Some questions on ratio and proportion, probability, and arrangement, time and work, time speed distance, number system. One can easily crack this section if one has practiced questions from any quantitative aptitude practice material. The aptitude part was such that many were able to crack it, but the technical part was the actual make or break part. The questions were vary basic questions but from a wide variety of areas such as electronics â€“ analog and digital. Questions on FET, BJT, MOS, K-map, microprocessor, networking etc, along with data structures, operating system, and algorithms were there. These questions touched the basic concepts of all the areas we had studied in our curriculum so far. Some of the questions I still remember: The data structure question was on inserting a node in middle of linked list, wherein we were given four options and we had to chose the correct code for the corresponding operations. The algorithms question was based on time complexity. Say there is a program whose time complexity is O(n^2.5), then which of the following can’t be true. Following this there were four statements, of which three said that the time would grow proportional to <=n^2.5. And one said that in some cases it may grow with n^2.6, which was definitely incorrect due to the time complexity being specified on Big-O notation which gives the upper bound on running time of the program. Question on simplify the expression, was easily doable with K-Map Question on determining the min number of NAND gates required to represent an expression with an expression being given in SOP form. Question on FET- which terminal of FET is forward biased and which is reversed? 27 got shortlisted in this round.