A Universal shift register is a register which has both the right shift and left shift with parallel load capabilities. Universal shift registers are used as memory elements in computers. A Unidirectional shift register is capable of shifting in only one direction. A bidirectional shift register is capable of shifting in both the directions. The Universal shift register is a combination design of **bidirectional** shift register and a **unidirectional** shift register with parallel load provision.

**n-bit universal shift register –**

A n-bit universal shift register consists of n flip-flops and n 4×1 multiplexers. All the n multiplexers share the same select lines(S1 and S0)to select the mode in which the shift register operates. The select inputs select the suitable input for the flip-flops.

**Basic connections –**

- The first input (zeroth pin of multiplexer) is connected to the output pin of the corresponding flip-flop.
- The second input (first pin of multiplexer) is connected to the output of the very-previous flip flop which facilitates the right shift.
- The third input (second pin of multiplexer) is connected to the output of the very-next flip-flop which facilitates the left shift.
- The fourth input (third pin of multiplexer) is connected to the individual bits of the input data which facilitates parallel loading.

The working of the Universal shift register depends on the inputs given to the select lines.

The register operations performed for the various inputs of select lines are as follows:

S1 | s0 | Register operation |
---|---|---|

0 | 0 | No changes |

0 | 1 | Shift right |

1 | 0 | Shift left |

1 | 1 | Parallel load |

**Reference:**

Digital Electronics – Atul P. Godse, Mrs. Deepali A. Godse

Attention reader! Don’t stop learning now. Get hold of all the important CS Theory concepts for SDE interviews with the CS Theory Course at a student-friendly price and become industry ready.

## Recommended Posts:

- Shift Registers in Digital Logic
- RTL (Register Transfer Level) design vs Sequential logic design
- Difference between Programmable Logic Array and Programming Array Logic
- Half Subtractor in Digital Logic
- Half Adder in Digital Logic
- Counters in Digital Logic
- Synchronous Sequential Circuits in Digital Logic
- Multiplexers in Digital Logic
- Full Adder in Digital Logic
- Full Subtractor in Digital Logic
- Binary Decoder in Digital Logic
- Encoder in Digital Logic
- Functional Completeness in Digital Logic
- Ripple Counter in Digital Logic
- BCD Adder in Digital Logic
- Consensus Theorem in Digital Logic
- n-bit Johnson Counter in Digital Logic
- Encoders and Decoders in Digital Logic
- Variable Entrant Map (VEM) in Digital Logic
- Static Hazards in Digital Logic

If you like GeeksforGeeks and would like to contribute, you can also write an article using contribute.geeksforgeeks.org or mail your article to contribute@geeksforgeeks.org. See your article appearing on the GeeksforGeeks main page and help other Geeks.

Please Improve this article if you find anything incorrect by clicking on the "Improve Article" button below.