Multiport Memory System employs separate buses between each memory module and each CPU. A processor bus comprises the address, data and control lines necessary to communicate with memory. Each memory module connects each processor bus. At any given time, the memory module should have internal control logic to obtain which port can have access to memory.
Memory module can be said to have four ports and each port accommodates one of the buses. Assigning fixed priorities to each memory port resolve the memory access conflicts. the priority is established for memory access associated with each processor by the physical port position that its bus occupies in each module. Therefore CPU 1 can have priority over CPU 2, CPU 2 can have priority over CPU 3 and CPU 4 can have the lowest priority.
High transfer rate can be achieved because of multiple paths
- It requires expensive memory control logic and a large number of cables and connectors.
- It is only good for systems with small number of processors.
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