Prerequisite – Cache Memory
A detailed discussion of the cache style is given in this article. The key elements are concisely summarized here. we are going to see that similar style problems should be self-addressed in addressing storage and cache style. They represent the subsequent categories: Cache size, Block size, Mapping function, Replacement algorithm, and Write policy. These are explained as following below.
- Cache Size:
It seems that moderately tiny caches will have a big impact on performance.
- Block Size:
Block size is the unit of information changed between cache and main memory.
As the block size will increase from terribly tiny to larger sizes, the hit magnitude relation can initially increase as a result of the principle of locality.the high chance that knowledge within the neck of the woods of a documented word square measure possible to be documented within the close to future. As the block size increases, a lot of helpful knowledge square measure brought into the cache.
The hit magnitude relation can begin to decrease, however, because the block becomes even larger and also the chance of victimization the new fetched knowledge becomes but the chance of reusing the information that ought to be abstracted of the cache to form area for the new block.
- Mapping Function:
When a replacement block of data is scan into the cache, the mapping performs determines that cache location the block will occupy. Two constraints have an effect on the planning of the mapping perform. First, once one block is scan in, another could be replaced.
We would wish to do that in such the simplest way to minimize the chance that we are going to replace a block which will be required within the close to future. A lot of versatile the mapping perform, a lot of scopes we’ve to style a replacement algorithmic rule to maximize the hit magnitude relation. Second, a lot of versatile the mapping perform, a lot of advanced is that the electronic equipment needed to look the cache to see if a given block is within the cache.
- Replacement Algorithm:
The replacement algorithmic rule chooses, at intervals, the constraints of the mapping perform, which block to interchange once a replacement block is to be loaded into the cache and also the cache already has all slots full of alternative blocks. We would wish to replace the block that’s least possible to be required once more within the close to future. Although it’s impossible to spot such a block, a fairly effective strategy is to interchange the block that has been within the cache longest with no relevance.
This policy is spoken because of the least-recently-used (LRU) algorithmic rule. Hardware mechanisms square measure required to spot the least-recently-used block
- Write Policy:
If the contents of a block within the cache square measure altered, then it’s necessary to write down it back to main memory before exchange it. The written policy dictates once the memory write operation takes place. At one extreme, the writing will occur whenever the block is updated.
At the opposite extreme, the writing happens only if the block is replaced. The latter policy minimizes memory write operations however leaves the main memory in associate obsolete state. This can interfere with the multiple-processor operation and with direct operation by I/O hardware modules.
Don’t stop now and take your learning to the next level. Learn all the important concepts of Data Structures and Algorithms with the help of the most trusted course: DSA Self Paced. Become industry ready at a student-friendly price.
- Concept of Cache Memory Design
- Locality of Reference and Cache Operation in Cache Memory
- Difference between Virtual memory and Cache memory
- Differences between Associative and Cache Memory
- Cache Memory in Computer Organization
- Memory Hierarchy Design and its Characteristics
- Difference between Random Access Memory (RAM) and Content Addressable Memory (CAM)
- Random Access Memory (RAM) and Read Only Memory (ROM)
- Introduction to memory and memory units
- What's difference between CPU Cache and TLB?
- LRU Cache Implementation
- Difference between Byte Addressable Memory and Word Addressable Memory
- Multilevel Cache Organisation
- DNS Spoofing or DNS Cache poisoning
- Types of Cache Misses
- Least Frequently Used (LFU) Cache Implementation
- Cache Organization | Set 1 (Introduction)
- Cache Coherence Protocols in Multiprocessor System
- Computer Organization | Locality and Cache friendly code
- Difference between Uniform Memory Access (UMA) and Non-uniform Memory Access (NUMA)
If you like GeeksforGeeks and would like to contribute, you can also write an article using contribute.geeksforgeeks.org or mail your article to email@example.com. See your article appearing on the GeeksforGeeks main page and help other Geeks.
Please Improve this article if you find anything incorrect by clicking on the "Improve Article" button below.