## GATE | GATE-CS-2003 | Question 60

A program consists of two modules executed sequentially. Let f1(t) and f2(t) respectively denote the probability density functions of time taken to execute the two… Read More »

## GATE | GATE-CS-2003 | Question 59

Consider the syntax directed definition shown below. S → id : = E {gen (id.place = E.place;);} E → E1 + E2 {t = newtemp… Read More »

## GATE | GATE-CS-2003 | Question 58

Consider the translation scheme shown below S → T R R → + T {print (‘+’);} R | ε T → num {print (num.val);} Here… Read More »

## GATE | GATE-CS-2003 | Question 90

Consider the grammar shown below. S → C C C → c C | d The grammar is (A) LL(1) (B) SLR(1) but not LL(1)… Read More »

## GATE | GATE-CS-2003 | Question 56

Consider the grammar shown below S → i E t S S’ | a S’ → e S | ε E → b In the… Read More »

## GATE | GATE-CS-2003 | Question 55

Consider the NFA M shown below. Let the language accepted by M be L. Let L1 be the language accepted by the NFA M1, obtained… Read More »

## GATE | GATE-CS-2003 | Question 54

Define languages L0 and L1 as follows : L0 = {< M, w, 0 > | M halts on w} L1 = {< M, w,… Read More »

## GATE | GATE-CS-2003 | Question 53

A single tape Turing Machine M has two states q0 and q1, of which q0 is the starting state. The tape alphabet of M is… Read More »

## GATE | GATE-CS-2003 | Question 52

Consider two languages L1 and L2 each on the alphabet ∑. Let f : ∑ → ∑ be a polynomial time computable bijection such that… Read More »

## GATE | GATE-CS-2003 | Question 90

Let G = ({S}, {a, b} R, S) be a context free grammar where the rule set R is S → a S b |… Read More »

## GATE | GATE-CS-2003 | Question 90

Consider the following deterministic finite state automaton M. Let S denote the set of seven bit binary strings in which the first, the fourth, and… Read More »

## GATE | GATE-CS-2003 | Question 49

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown… Read More »

## GATE | GATE-CS-2003 | Question 48

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown… Read More »

## GATE | GATE-CS-2003 | Question 47

Consider the following circuit composed of XOR gates and non-inverting buffers. The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns… Read More »

## GATE | GATE-CS-2003 | Question 90

Consider the ALU shown below. If the operands are in 2’s complement representation, which of the following operations can be performed by suitably setting the… Read More »