Prerequisites: 8259 PIC
8259 PIC is designed for the 8085 and 8086 microprocessor’s series.
Need For PIC in 8085 and 8086 :
- In 8086 we have two pins for interrupt handling i.e. NMI and INTR. If we use NMI for data corruption or non-recoverable hardware errors and one interrupt pin, INTR for other software interrupts.
- In a system when we have multiple interrupts from different input or output devices, then we need a PIC(priority interrupt controller) that can handle multiple interrupts from different devices and prioritize them according to system requirements, and sends them to a single interrupt pin on the processor.
Characteristics of 8259 :
- A single 8259 handles 8 interrupts, while a cascaded configuration of it in which 1 master and 8 slaves can handle up to 64 interrupts.
- It can handle both edge-level triggering interrupts.
- Its priority structure can be easily altered.
- In 8259, interrupts can be masked individually.
- The vector address of the interrupts is easily programmed.
- It must be initialized by giving commands, to determine various properties like vector numbers, priority, masking, triggering etc.
Operating modes of 8259 :
The different modes of operation of 8259 can be programmed by altering the bits of ICW or OCW commands of 8259.
Fully nested mode :
- It is the default mode of operation of 8259.
- Here, IR0 has the highest priority and IR7 has the lowest priority. When any interrupt requests occurs then the highest priority interrupt request is serviced first and its vector address is placed on data bus and its corresponding bit in ISR register is set until the processor executes the EOI command before returning the interrupt service routine or AEOI(Automatic end of interrupt bit is set) until the falling of the last INTA’.
- When the ISR bit is set for an interrupt, then all the equal and lower priority interrupts are masked, but a higher level interrupt request can occur and which will be acknowledged only if the microprocessor interrupt enables flag IF= 1.
- It is suitable for a single 8259 configuration.
- The priority mechanism can be easily programmed.
Special fully nested mode (SFNM) :
This mode is used by master 8259 in a cascaded mode. Its priority structure is fixed and is the same as fully nested mode (i.e. IR0 has the highest priority and IR7 has the lowest priority).
In a special fully nested mode, the master will only serve higher priority interrupt from a slave, whose another interrupt is currently in service.
Rotating priority modes :
There are two rotating priority modes –
1. Automatic rotation mode
- It is used when various interrupt sources are of the same priority. In this mode, after a device is serviced, it gets the lowest priority. All other priorities rotate according to it.
- Example: If IR4 has just been serviced, it will get the lowest priority.
2. Specific Rotation Mode
- Here, the programmer can alter priorities by programming the lowest priority and thus fixing all other priorities.
- For example: If IR6 is programmed as the lowest priority, then IR7 will have the highest priority.
Special mask mode (SMM) :
- In SMM, 8259 enables interrupts of all levels (lower or higher) except the one that is currently in service.
- Because we are especially masking the request of the priority level of interrupt, which is the same as the current interrupt priority level, therefore it is called special mask mode.
Poll mode :
Here the INT pin of 8259 is not used, so, 8259 cannot interrupt the µp. Instead, the µP will provide a poll command to 8259 using OCW3. In response, 8259 provides a poll word to the µP. The poll word indicates the highest priority interrupt which needs service from µP. Thereafter, the µP services the interrupt.
The µP’s program is not interrupted. It can be used when ISR is common for many interrupts. It can be used to increase the number of interrupts beyond 64(i.e. in case of a cascaded configuration).
If the polling interval is long, then the interrupts will be serviced after a long period. If the polling interval is short, then the time may be wasted on unnecessary polls.
EOI – (End Of Interrupt) :
When the microprocessor acknowledges an interrupt request by sending the first INTA signal, the 8259 sets the corresponding bit in the In Service Register (ISR). This starts the service of the interrupt.
When this bit in the ISR is cleared, then it is known as the end of interrupt (EOI).
1. Normal EOI Mode –
Here, an EOI command is compulsory. The EOI command is written by the programmer at the end of the ISR. It makes 8259 to reset the bit from ISR. Further EOI command is of two types :
- Non Specific EOI Command Here the programmer doesn’t specify the bit number to be reset in the ISR. 8259 itself resets the highest priority bit from ISR.
- Specific EOI Command: Here the programmer determines the bit number to be reset from ISR.
2. Automatic EOI mode (AEOI) –
In this mode, the EOI command is not required. Instead, 8259 will itself clear the corresponding bit from ISR at the end of the 2nd INTA pulse.
Edge and level-triggered mode :
If the LTIM bit of ICW1 =0 then the edge-triggered interrupt mode is set, otherwise the interrupts are level triggered.
Reading 8259 Status :
The status of the registers can be read by this mode. Here, the OCW3 is used to read IRR and ISR and OCW1 is used to read IMR.
Buffered Mode :
8259 sends a buffer enabled signal on the SP’/ EN’ pin when data is placed on the data bus.
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