Asynchronous Communication Interface
The block diagram of the asynchronous communication interface is shown above. It functions both as a transmitter and receiver.
Parts of the Interface :
The interface is initialized by the help of control bit loaded into the control register. The transmitter register accepts the data byte from CPU through data bus which is then transferred to shift register for serial transmission. The serial information is received into another shift register and is transferred to the receiver register when a complete data byte is accumulated. The bits in status register are used to check any errors during transmission and for input and output flags which can be read by the CPU. The chip select (CS) input is used to select interface through address bus. The register select (RS) is associated with Read (RD) and write (WR) controls. Two registers are read and write only.
The register selected is the function of RS value and RD and WR status as shown in the table below.
Working of the interface :
The interface is initialized by the CPU by sending a byte to the control register. Two bits in the status register are used as flags and one bit is used to indicate whether the transmission register is empty and another bit is used to indicate whether the receiver register is full.
Working of the transmitter portion :
The CPU reads the status register and checks the transmitter. If the transmitter is empty then CPU transfers the character to transmitter. The first bit in transmitter is set to 0 to generate a start bit. The parallel transfer of character takes place from the transmitter register to the shift register. The transmitter is then marked empty. The CPU can transfer another character to transmitter register after checking the flag in status register.
Working of receiver portion :
The receive data input is in 1-state when line is idle. The receiver control monitors the receive data line to detect the occurrence of a start bit. The character bits are then shifted to the shift register once the start bit has been detected. When the stop bit is received, the character is transferred in parallel from shift register to the receiver register.
The interface checks for any errors during transmission and sets appropriate bits in the status register. The three possible errors that the interface checks are the parity error, framing error and over run error.