Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative
organization is h1 while that of the direct mapped one is h2.

The value of h2 is:
(A) 2.4 ns
(B) 2.3
(C) 1.8
(D) 1.7


Answer: (D)

Explanation: Cache size = 32 KB = 32 * 2¹⁰ bytes
Cache block size = 32 bytes
Number of blocks = 1

Total combinations are :
= cache size / (Number of blocks * block size)
= 32 * 2¹⁰ / (1 * 32)
= 1024
= 2¹⁰

Therefore, number of index bits = 10

Since, cache block size is 32 bytes i.e. 2⁵ bytes.
Number of offset bits = 5

So, number of tag bits = 32 – 10 – 5 = 17

Hit latency (h2) = (17 / 10) ns = 1.7 ns

 
Thus, option (D) is correct.

 
Please comment below if you find anything wrong in the above post.


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