Qualcomm Interview Experience (On-Campus)

Qualcomm had come to my University for two roles – Hardware and Software. I applied for Hardware Role. There was one round of online tests and 2 interview rounds.

Round 1 (Online Test): It consisted of 3 sections with 20 questions in each section and 30 mins per section. You can travel through the questions in a particular section. The marking scheme was +1 for the correct answer and -0.25 for the wrong answer. Approximately 1500 people gave the test for both software and hardware role.

• The first section was aptitude questions which involved easy to medium-difficulty logical, aptitude, and simple math-based questions.
• The second section was based on C programming and had output-based MCQs along with some number system questions.
• The third section had a choice between CS and Digital. I selected the Digital section as I had applied for the Hardware role. It consisted of Digital Electronics with questions from Combinational and Sequential circuits, Boolean algebra, CMOS, BJT, ADC, DAC, etc.

After 2 days of the online test, around 35 people were selected for the interview process.

Round 2 (Interview 1): This was a technical interview and it went on for around 50 mins. It was conducted online on Microsoft Teams. I had a blank piece of paper ready with me for writing down/drawing answers for some questions as well as performing rough work. The interview covered quite a lot of topics and the questions asked in the interview were:

• A few questions about my resume.
• Draw transfer characteristics of the inverter.
• What is the threshold voltage of an inverter?
• What is high and low Noise margin? What does it signify
• Draw the CMOS inverter and mark all 4 terminals.
• Draw a physical diagram of an NMOS.
• What happens if the body is not shorted to the source? What might happen if it is connected to a higher voltage than the source?
• What are state machines?
• Write the Verilog code for a mod-3 counter.
• What are the common mistakes one can make while writing this Verilog code?
• How would you make an AND gate with a 2×1 MUX?
• How would you make an OR gate with an XOR gate?

I was able to answer almost all questions barring a few. A few people were removed after this round.

Round 3 (Interview 2): This was also a technical interview mainly except for a few discussions about location preferences. This again was conducted online on Microsoft Teams, the same day as the first interview. It lasted for about 35-40 mins. The questions asked were:

• Asked a few general and personal questions about me and my resume.
• A logical aptitude-based question – If you have 2 cubes with 6 surfaces each, how will you display any day of a month from 01 to 31 using the 2 cubes by writing any single digit number on each side of both the cubes?
• Implement an OR gate using NAND gates.
• Draw an OR gate using a 2×1 MUX.
• What is the equation of an EXOR gate?
• Draw a NAND gate using CMOS logic.
• Explain how it functions.
• What are the setup time and hold time?
• What are the different types of Finite state machines? What is the difference?
• Draw the state diagram of a sequence detector to detect – 01*0010*1 – where 1* means that 1 can be repeated any number of times and similarly 0*.
• Verbally explain how you would write a Verilog code for a finite state machine.
• Discussions regarding job location.

After the second round, there was no further HR round for any of the applicants. The same day we received the final results of the process and in total 8 people were selected for an Internship + Full-time offer. Out of these, 4 were for Hardware and 4 were for Software.