MOTOROLA 680X0 and COLDFIRE Processor Families
68000 processor was introduced in 1979. Through 1980’s and early 1990’s the 68000, 68020, 68030 and 68040 were targeted for personal computer’s market and were used for Apple computers. Latest member of 680X0 family is 68060, introduced in mid-1990’s. 68060 and the closely related ColdFire family are targeted for the embedded system market. First we will go through 68020 processors.
1. 68020 Processor :
68020 is more powerful than the 68000, mainly because of some significant architectural enhancements. These advances were made possible by improved VLSI technology and large packages that removed many constraints of pin limitations. 68020 has external connections for 32-bit addresses and 32-bit data. Although its data bus is 32 bits wide, 68020 can deal efficiently with devices that transfer 8, 16 or 32 bits a time. Processor can adjust dynamically to the data bus width requirements of a particular device in a manner that is transparent to any programmer. 68020 bus includes control lines that are activated by the devices connected to the bus to indicate required size of their data transfers. Thus, processor can deal with devices of different data transfer sizes without knowing the actual size before a data transfer is initiated.
68000 restriction that word operands must be aligned on even address boundaries has been eliminated in 68020; operands of any size may start at any address. This means that 16 and 32-bit operands can occupy parts of two adjacent 32-bit locations in memory. Two access cycles are therefore needed to reach such operands and this affects performance. Processor automatically performs these two accesses. From the address, processor knows which 32-bit locations must be accessed and in what pattern the individual bytes from these locations should be assembled to obtain desired operand.
Register Set & Data Types –
Like 68000, 68020 has user and supervisor modes of operations. In supervisor mode, the 68020 allows quad word, unpacked BCD and bit-field data types. A quad word consists of 64 bits and unpacked BCD has one BCD digit per byte. A bit field consists of a variable number of bits in a 32-bit long word and it is specified by the location of its leftmost bit and number of bits in field.
Addressing Modes –
68020 processors have some extra addressing modes than 68000 so that they can be more flexible and allow efficient access to data and address list structures. Full indexed mode is the most powerful as it allows a range of offsets and provides for a scaling factor. The 68020 version of this allows displacement to be 8, 16 or 32 bit value. It also introduces scale factor by which the contents of Rk are multiplied. The value of scale factor may be 1,2,4 or 8. The syntax for code is:
Here An is Register Indirect (one of the addressing modes).
We noticed that displacement is given within the parenthesis in the above code. So effective address EA is:
EA = disp + [An] + ( [Rk] x scale )
This mode is useful when dealing with lists of items that are 1,2,4 or 8 bytes long. If this scale factor is chosen so that it equals to size of the items, then successive items in the list can be accessed by incrementing the contents of Rk by 1.
Another powerful extension of indexed addressing is the memory indirect indexed modes, in which an address operand is obtained indirectly from the main memory. Two such mode exists.
In memory indirect postindexed mode, address is fetched from the memory before normal indexing process takes place.The effective address is computed as
EA = [basedip + [An]] + ([Rk] x scale) + outdip
Note that two displacements are used. A base displacement of 16 or 32 bits is used to modify the address in An, which is used to fetch address operand from the memory. This allows an address to be selected from a list of address stored in memory starting at some location given by the contents of An. The second displacement s the normal displacement used in indexing addressing, called outer displacement to distinguish it from the base displacement.
In memory indirect preindexed mode, most of the indexing modification is done before address operand is fetched. Syntax for this mode is:
([basedip,An,Rk.size*scale],outdip) and then EA = [basedip + [An] + ([Rk] x scale)] + outdip
In both of the above discussed modes, value of An, Rk, basedip and outdip are optional and are not included in the computation of the effective address unless specified by the user. These addressing modes are useful for dealing with lists in which contiguous memory locations are used to store addresses of data items, rather than the data items themselves. The latter can be anywhere in the memory.
Instruction Set –
All 68000 instructions are available in 68020. Some have extra flexibility. For example, branch instructions can have 32-bit displacements and several instructions have the option of using longer operands. Some new instructions are also provided such as Instructions that deal with bit-field operands.
On-Chip Cache –
68020 chip includes a small instruction cache that has 256 bytes organized as 64-long word blocks. A direct mapping scheme is used when loading new words into cache.
2. 68030 & 68040 Processor :
There are two major different aspects in 68030 than 68020. In addition to the instruction cache, 68030 has another cache of the same size for data. Data cache organization has 16 blocks of 4 long words each. 68030 also contains a memory management unit (MMU).
The execution in the 68030 generates virtual address. Cache access circuit determines if the desired operand is in the cache, based on virtual address. The MMU translates the virtual address into a physical address in parallel with the cache access so that, in case of a cache access miss, th ephysical address needed to access the operand if the main memory is immediately available.
68040, includes a floating – point unit that implements IEEE floating point standards. 68040 has the following things:
- Memory management is improved over that in the 68030; 68040 has two independent address translation caches that permit simultaneous translation of addresses for both instruction and data.
- It has a pipeline structure that permits fetching of instructions while previous instructions are still being processed.
- Two internal buses are used to transfer instructions and data from respective caches. They also allow simultaneous access to instruction and data caches.
- It includes circuit that monitor activity on external bus. Thus, this makes 68040 suitable for use in multiprocessor systems.
3. 68060 Processor :
Latest member of 680X0 family is 68060 , Introduced in mid 1990’s, with clock rates ranging from 50 – 75 MHz. This processor is intended for the embedded system market. New organizational and favrication features results in performance that is 2.5 times that of a 40 MHz 68040. 68080 is a pipelined super-scalar processor. Pipeline has 04 basic stages, with an additional two stages (if a memory writeback operation is required). Upto 03 instruction can be initiated per block cycle. 03 function units – integer units and a floating point unit – comprise the main instruction processing hardware. There are separate, on-chip, 8K byte instruction and data caches. Each cache is a 4 way set associative and uses 16 bytes block. Two 64 entry, 4 way, set-associative, translation lookaside buffers to facilitate virtual to physical address translation are provided with the caches. Dynamic branch prediction is used to enhance smooth flow of instructions through pipeline.
4. COLDFIRE Processor Families :
Since mid 1990’s, Motorola has produced a series of processor components and small computer configurationism called the ColdFire family, that is targeted for the embedded system market. Processors are based on the 68060 processor core. A number of different products are configured with small amount of memory and I/O port hardware for parallel and serial connections. These products meet a range of power and performance requirements for different applications. Both hardware chip products and synthesizable software designs are available in the ColdFire Family.