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ARM Interrupt Structure

Last Updated : 18 Nov, 2022
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A collection of reduced instruction set computer (RISC) instruction set architectures for computer processors that are tailored for different contexts is known as ARM (stylized in lowercase as an arm; originally an abbreviation for Advanced RISC Machines. System-on-a-chip (SoC) and system-on-module (SOM) designs, which combine various components including memory, interfaces, and radios, are examples of devices that other firms design and manufacture using one or more of the architectures that ARM Ltd. develops and licenses. Additionally, it develops cores that use these instruction set architectures and licenses these designs to a large number of businesses, who then use them to create their own products.

The ARM design has gone through multiple iterations. The original ARM1 featured a 32-bit internal structure but only supported 64 MB of main memory due to its 26-bit address space. The ARMv3 series, which has a 32-bit address space, abolished this restriction, while subsequent generations up to ARMv7 maintained this constraint. With its new 32-bit fixed-length instruction set, the 2011-released ARMv8-A architecture gained capability for 64-bit address space and 64-bit arithmetic. Arm Ltd. also released a number of additional instruction sets for various rules. Simultaneous multithreading (SMT) has been added more recently for fault tolerance or improved performance. 

For light, portable, battery-powered devices like smartphones, laptops, and tablet computers, as well as other embedded systems, ARM processors are preferred because they are less expensive, consume less power, and generate less heat than their competitors. However, ARM processors are widely employed in servers and desktop computers, notably Fukuku, which will hold the record for the fastest supercomputer from 2020 until 2022. As of 2022, ARM will have created over 230 billion ARM chips, making it the most popular and most abundant family of instruction set architectures (ISA). To include or exclude optional capabilities, there are currently variants of the popular Cortex cores, older “classic” cores, and specialized SecurCore cores available for each of these.

Structure of ARM interrupt:

The following points help us in understanding the structure of ARM interrupt:

  • All interrupts are disabled on startup for the ARM CPU until the initialization code turns them on. The Processor Status Registers’ bit can be changed to enable or disable the interrupts (PSR or CPSR where C stands for current). The CPSR also determines whether the processor is decoding Thumb instructions and the processor mode (SVC, System, User, etc.). The application can read and write to the CPSR in its entirety when operating in privileged mode, but it can only read the CPSR when operating in non-privileged mode. The processor enters the appropriate interrupt or exception mode in response to an interrupt or exception, which causes a portion of the main registers to be banked, swapped out, or replaced with set mode registers.
  • The interrupt masks’ ability to be enabled and disabled is controlled by bits. The two interrupt inputs on the ARM processor can both be regarded as general-purpose interrupts. Interrupt Request (IRQ) and Fast Interrupt Request are the names of the first and second, respectively (FIQ)
  • The regular sequential execution of instructions can be stopped by one of seven events on the ARM processor. Since not all events are created equal, the processor must adopt a priority strategy because these events may occur simultaneously. For instance, since it happens when the power to the ARM processor is switched, the Reset has the highest priority. As a result, a reset supersedes all other events when it happens. The only exception to this rule is a Reset event, which takes precedence over all other events when a Data Abort occurs. Since the ARM processor must recognize the event with the highest importance when several events are happening at once, this priority mechanism is crucial.
  • The vector table begins at 0x00000000, as was indicated in earlier chapters (ARMx20 processors can optionally locate the vector table address to 0xffff0000). A vector table is a collection of ARM instructions that control the computer (i.e. B, MOV, and LDR). These commands cause the computer to jump to a certain area that can deal with a particular exception or interrupt. Since the FIQ vector is at the end of the table, it can avoid using the B or LDR instruction. The FIQ handler can now begin execution at the FIQ vector point. By preventing the pipe from having to be flushed when the PC is moved, FIQs can conserve processor cycles.
  • From an interrupt handler returning The return address from an interrupt or execution handler must be changed because of the processor pipeline. An offset will be present in the address that is kept in the link register. As a result, the offset value must be deducted from the link register.
  • The interrupt stacks being set up Depending on the hardware being utilized and the RTOS needs, the interrupt stack may be put in a different location. The target system will crash if the Interrupt Stack extends into the Interrupt vector. Unless a check is made on the stack’s extension and a way is provided to deal with that problem when it happens. The IRQ mode stack must first be set up before an interrupt may be enabled. Normally, this is completed in the system’s initialization code. Knowing the stack’s maximum size is crucial because it allows for the interrupt stack to be allocated that much space. Possible memory configurations with a linear address space are shown below.
  • Interrupt handler installation and chaining. The vector table can be fixed for ROM and/or FlashROM-based devices without the need for installation. These systems often copy the entire vector table from ROM to RAM as a block without the need to install individual vectors. Since memory tends to be remapped during initialization, this method is typically employed. Placing a vector entry for the IRQ address (0x00000018) or FIQ address (0x0000001C) so that the entry links to the proper handler is the first step in installing an interrupt handler. Chaining entails inserting a new entry while saving the current vector entry. The original handler may regain control if the newly added handler is unable to handle a certain interrupt source by calling the saved vector entry.
  • Another interrupt may occur inside the presently called handler thanks to nested interrupt handlers. This is accomplished by re-enabling the interrupts before the current interrupt has been fully handled by the handler. This feature makes the system more complex for real-time systems. A system failure could result from subtle timing problems introduced by this complexity. These small issues can be very challenging to fix. In order to prevent issues of this nature, the nested interrupt technique needs to be carefully constructed. In order to prevent the next interrupt from filling (overflowing) the stack or corrupting any of the registers, context restoration is protected from interruption.
  • If nested interrupts are supported, many common issues can be seen as a result of a rise in complexity. A race condition that results in a cascade of interrupts is one of the key issues. The handler will experience constant interruptions up until the point at which the interrupt stack overflows or the registers become damaged. When designing, efficiency and safety must be balanced. This entails writing code defensively, assuming issues will arise. When possible, the system should examine the stack and take precautions to prevent register corruption.
  • Multiple interrupts can be handled using a re-entrant interrupt handler, where interruptions are prioritized. This is significant because interrupts with a higher priority must have a smaller latency. The typically nested interrupt handler is unable to perform this kind of filtering. Re-enabling interrupts early on in the interrupt handler to achieve minimal interrupt latency is the primary distinction between a re-entrant interrupt handler and a nested interrupt handler.
  • A prioritized interrupt handler will assign a priority level to a specific interrupt source as opposed to the simple and nested interrupt handlers, which service interruptions on a first-come, first-served basis. The sequence in which the interrupts are handled is determined by a priority level. A desirable property in an embedded system is that a higher-priority interrupt will take precedence over a lower-priority interrupt.

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