Prerequisite – Multilevel Cache Organisation
Cache is a technique of storing a copy of data temporarily in rapidly accessible storage memory. Cache stores most recently used words in small memory to increase the speed in which a data is accessed. It acts like a buffer between RAM and CPU and thus increases the speed in which data is available to the processor.
Whenever a Processor wants to write a word, it checks to see if the address it wants to write the data to, is present in the cache or not. If address is present in the cache i.e., Write Hit.
We can update the value in the cache and avoid a expensive main memory access.But this results in Inconsistent Data Problem.As both cache and main memory have different data, it will cause problem in two or more devices sharing the main memory (as in a multiprocessor system).
This is where Write Through and Write Back comes into picture.
In write through, data is simultaneously updated to cache and memory. This process is simpler and more reliable.This is used when there are no frequent writes to the cache(Number of write operation is less).
It helps in data recovery (In case of power outage or system failure). A data write will experience latency (delay) as we have to write to two locations (both Memory and Cache). It Solves the inconsistency problem. But it questions the advantage of having a cache in write operation (As the whole point of using a cache was to avoid multiple accessing to the main memory).
The data is updated only in the cache and updated into the memory in later time. Data is updated in the memory only when the cache line is ready to replaced (cache line replacement is done using Belady’s Anomaly, Least Recently Used Algorithm, FIFO, LIFO and others depending on the application).
Write Back is also known as Write Deferred.
Dirty Bit : Each Block in the cache needs a bit to indicate if the data present in the cache was modified(Dirty) or not modified(Clean).If it is clean there is no need to write it into the memory. It designed to reduce write operation to a memory. If Cache fails or if System fails or power outage the modified data will be lost. Because its nearly impossible to restore data from cache if lost.
If write occurs to a location that is not present in the Cache(Write Miss), we use two options, Write Allocation and Write Around.
In Write Allocation data is loaded from the memory into cache and then updated. Write allocation works with both Write back and Write through.But it is generally used with Write Back because it is unnecessary to bring data from the memory to cache and then updating the data in both cache and main memory. Thus Write Through is often used with No write Allocate.
Here data is Directly written/updated to main memory without disturbing cache.It is better to use this when the data is not immediately used again.
Attention reader! Don’t stop learning now. Get hold of all the important DSA concepts with the DSA Self Paced Course at a student-friendly price and become industry ready.
- Differentiate between Write Through and Write Back Methods
- Journaling or write-ahead logging
- Read and Write operations in Memory
- Ways to write N as sum of two or more positive integers | Set-2
- Thomas Write Rule in DBMS
- How to read and write JSON file using Node.js ?
- Main difference between Timestamp protocol and Thomos write rule in DBMS
- Locality of Reference and Cache Operation in Cache Memory
- Step by Step guide to Write your own WordPress Template
- What's difference between CPU Cache and TLB?
- LRU Cache Implementation
- DNS Spoofing or DNS Cache poisoning
- Cache Memory Design
- Types of Cache Misses
- Multilevel Cache Organisation
- Cache Organization | Set 1 (Introduction)
- Back-off Algorithm for CSMA/CD
- Design a data structure for LRU Cache
If you like GeeksforGeeks and would like to contribute, you can also write an article using contribute.geeksforgeeks.org or mail your article to email@example.com. See your article appearing on the GeeksforGeeks main page and help other Geeks.
Please Improve this article if you find anything incorrect by clicking on the "Improve Article" button below.
Improved By : aish623n