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Translation Lookaside Buffer (TLB) in Paging

Last Updated : 16 Apr, 2024
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In Operating System (Memory Management Technique: Paging), for each process page table will be created, which will contain a Page Table Entry (PTE). This PTE will contain information like frame number (The address of the main memory where we want to refer), and some other useful bits (e.g., valid/invalid bit, dirty bit, protection bit, etc). This page table entry (PTE) will tell where in the main memory the actual page is residing. 

Now the question is where to place the page table, such that overall access time (or reference time) will be less. The problem initially was to fast access the main memory content based on the address generated by the CPU (i.e. logical/virtual address). Initially, some people thought of using registers to store page tables, as they are high-speed memory so access time will be less. 

The idea used here is, to place the page table entries in registers, for each request generated from the CPU (virtual address), it will be matched to the appropriate page number of the page table, which will now tell where in the main memory that corresponding page resides. Everything seems right here, but the problem is registered size is small (in practice, it can accommodate a maximum of 0.5k to 1k page table entries) and the process size may be big hence the required page table will also be big (let’s say this page table contains 1M entries), so registers may not hold all the PTE’s of the Page table. So this is not a practical approach. 

The entire page table was kept in the main memory to overcome this size issue. but the problem here is two main memory references are required: 

  1. To find the frame number 
  2. To go to the address specified by frame number 

To overcome this problem a high-speed cache is set up for page table entries called a Translation Lookaside Buffer (TLB). Translation Lookaside Buffer (TLB) is a special cache used to keep track of recently used transactions. TLB contains page table entries that have been most recently used. Given a virtual address, the processor examines the TLB if a page table entry is present (TLB hit), the frame number is retrieved and the real address is formed. If a page table entry is not found in the TLB (TLB miss), the page number is used as an index while processing the page table. TLB first checks if the page is already in main memory, if not in main memory a page fault is issued then the TLB is updated to include the new page entry. 


Steps in TLB hit

  1. CPU generates a virtual (logical) address. 
  2. It is checked in TLB (present). 
  3. The corresponding frame number is retrieved, which now tells where the main memory page lies. 

Steps in TLB miss

  1. CPU generates a virtual (logical) address. 
  2. It is checked in TLB (not present). 
  3. Now the page number is matched to the page table residing in the main memory (assuming the page table contains all PTE). 
  4. The corresponding frame number is retrieved, which now tells where the main memory page lies. 
  5. The TLB is updated with new PTE (if space is not there, one of the replacement techniques comes into the picture i.e either FIFO, LRU or MFU etc).

Effective memory access time(EMAT)

 TLB is used to reduce adequate memory access time as it is a high-speed associative cache. 

[Tex]EMAT = h \times (c + m) + (1 – h) \times (c + nm) [/Tex]


  • h is the hit ratio of the TLB,
  • m is the memory access time,
  • c is the TLB access time, and
  • n represents the system level.
    System level would be: * 1 –> No page table. * 2 –> One page table. * 3 –> Two page tables (directory and table). etc.


1. What happens when a process tries to access a page that is not present in the main memory or in the TLB?


When a process generates a virtual address that does not correspond to a page in the main memory or in the TLB, a page fault occurs. This means that the operating system needs to retrieve the missing page from secondary storage (e.g., hard disk) and bring it into the main memory. Once the page is in the main memory, the TLB is updated to include its corresponding PTE.

2. Can multiple processes share the same physical memory frame?


Yes, it is possible for multiple processes to share the same physical memory frame. This is known as page sharing or page deduplication, and it can be useful to reduce memory usage and improve system performance. However, page sharing needs to be carefully managed to ensure data integrity and security.

3. What are some standard replacement policies used by TLBs?


TLBs typically use either a Least Recently Used (LRU) or a First-In-First-Out (FIFO) replacement policy. LRU means that the TLB entry that has not been used for the longest time is replaced, while FIFO means that the TLB entry that was first inserted is replaced. Other possible policies include Most Recently Used (MRU), Most Frequently Used (MFU), and Random.

4. Why translation look-aside buffers are necessary?


Each process in an operating system has its own page table. Additionally, a PTE is present in each page table. The location of the actual page in the main memory is disclosed by a PTE. Additionally, it contains bit information such as dirty bits, protection bits, valid or invalid bits, etc. The PTE also contains the frame number, which is the address of the main memory being referred to. To cut down on overall time for access as much as possible, the page table and its PTEs must be located somewhere.

5. What benefits and drawbacks of translation look-aside buffers?


A memory type called a TLB is faster and smaller than main memory while also being more affordable and larger than a register. The speed is increased when a memory address is saved in the TLB and can be retrieved from there. This is so that the CPU doesn’t need to repeatedly access the main memory to access the page table. Instead, because the TLB is closer to the CPU, it can access it more quickly.

TLBs additionally offer the assistance needed for multiuser computers to maintain memory segregation through the use of a user and supervisor mode as well as permissions on read/write bits to enable sharing.

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