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Tag Archives: GATE-Gate IT 2007

Consider the following finite automata P and Q over the alphabet {a, b, c}. The start states are indicated by a double arrow and final… Read More
Consider the following grammars. Names representing terminals have been specified in capital letters. Which one of the following statements is true? (A) G1 is context-free… Read More
Consider the grammar given below S → x B | y A A → x | x S | y A A B → y… Read More
Consider the following DFA in which s0 is the start state and s1, s3 are the final states. What language does this DFA recognize ?… Read More
The two grammars given below generate a language over the alphabet {x, y, z} Which one of the following choices describes the properties satisfied by… Read More
The line T in the following figure is permanently connected to the ground. Attention reader! Don’t stop learning now.  Practice GATE exam well before the… Read More
A hard disk system has the following parameters : Number of tracks = 500 Number of sectors/track = 100 Number of bytes /sector = 500… Read More
An error correcting code has the following code words: 00000000, 00001111, 01010101, 10101010, 11110000. What is the maximum number of bit errors that can be… Read More
(C012.25)H – (10111001110.101)B = (A) (135103.412)o (B) (564411.412)o (C) (564411.205)o (D) (135103.205)o Answer: (A) Explanation: (C012.25)H – (10111001110.101)B = 1100 0000 0001 0010. 0010 0101… Read More
Following table indicates the latencies of operations between the instruction producing the result and instruction using the result. Attention reader! Don’t stop learning now.  Practice… Read More
What is the final value stored in the linear feedback shift register if the input is 101101? (A) 0110 (B) 1011 (C) 1101 (D) 1111… Read More
Data forwarding techniques can be used to speed up the operation in presence of data dependencies. Consider the following replacements of LHS with RHS. In… Read More
The following expression was to be realized using 2-input AND and OR gates. However, during the fabrication all 2-input AND gates were mistakenly substituted by… Read More
Consider a Direct Mapped Cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, 8,… Read More
The floating point unit of a processor using a design D takes 2t cycles compared to t cycles taken by the fixed point unit. There… Read More

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