ISRO | ISRO CS 2018 | Question 21

In the diagram above, the inverter (NOT gate) and the AND-gates labeled 1 and 2 have delays of 9, 10 and 12 nanoseconds(ns), respectively. Wire delays are negligible. For certain values of a and c, together with certain transition of b, a glitch (spurious output) is generated for a short time, after which the output assumes its correct value. The duration of the glitch is

(A) 7 ns
(B) 9 ns
(C) 11 ns
(D) 13 ns


Answer: (A)

Explanation:

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