A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be
(A) 120.4 microseconds
(B) 160.5 microseconds
(C) 165.5 microseconds
(D) 590.0 microseconds
Delay between each stage is 5 ns. Total delay for 1st data item = 165*4 = 660 For 1000 data items, first data will take 660 ns to complete and rest 999 data will take max of all the stages that is 160 ns + 5 ns register delay Total Delay = 660 + 999*165 ns which is equal to 165.5 microsecond.
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