A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S – R * (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.
The IF, ID and WB stages take 1 clock cycle each. The EX stage takes 1 clock cycle each for the ADD, SUB and STORE operations, and 3 clock cycles each for MUL and DIV operations. Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is
Pipelining is a technique in which the instructions are performed in parallel by executing different phases of the instructions.
Generally, if two operations are performed in which second operation has dependent operands on first then, the second should not fetch operands until the first one executes as it will otherwise fetch incorrect operands. Hence, stalls are created .
Now to overcome this , operand forwarding technique was introduced in which there is an interface through which the operand results are transferred. So, even if the incorrect operands were fetch during the fetch operations during the execution phase the incorrect operands are replaced by the
Thus,in the given question,though MUL is dependent on ADD due to R5,SUB is dependent on MUL due to R6 DIV is dependent on SUB and STORE dependent on DIV still we can perform Instruction fetch and decode operations in the pipelined processor.
As shown in the table 12 clock cycles will be taken to perform the given instructions.
This solution is contributed by Shashank Shanker khare