Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5- stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is __________ .
Note – This question was Numerical Type.
Explanation: Assume the total number of instructions to be ‘m’.
For a non-pipelined processor:
It takes 5 clock cycles to complete an instruction operating at 2.5GHz.
One clock cycle time=1/(2.5*109)= 0.4ns
For m instructions total number of clock cycles required= 5m.
Time taken to complete 5m clock cycles= 0.4*5m= 2m ns
For a pipelined processor:
Pipeline is 5-staged, Overheads associated with pipelining force to operate the pipelined processor at 2 GHz.
One clock cycle time= 1/(2*109)= 0.5ns
For m instructions total number of clock cycles required= 0.3m*(0.05*(50+1)+0.95*(1))+0.6m*(1)+0.1m*(0.5*(2+1)+0.5*(1))= 1.85m.
Time taken to complete 1.85m clock cycles= 0.5*1.85m= 0.925m ns
Speedup= Time taken without pipelining/Time taken with pipelining
= 2m ns/ 0.925m ns
This solution is contributed by Vinay Kumar Sajja
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