GATE | GATE-CS-2016 (Set 2) | Question 43

• Last Updated : 30 Sep, 2021

Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies v1, v2, and v3 such that
v1 = 3v2/4 = 2v3. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is _________ GHz, ignoring delays in the pipeline registers
(A) 2
(B) 4
(C) 8
(D) 16

Explanation: Ans is B

Consider this pipeline
(V1) --> (V2) --> (V3)
Can be written as
(V) --> (4V/3) --> (V/2)
Where given V = V1 = 3V2/4 = 2V3

Largest stage is stage 2 with 4V/3 seconds time required. Speed of processor is limited by this stage only. In fact this is the speed of the processor.

Frequency given is 3Ghz, which means processor can execute

3 Giga clock cycle.... in 1 second
Or
1 clock cycle .....in (1/3G) secs
(G for giga)

But we know that stage latency of the largest stage in pipeline limits the time of 1 clock cycle. Hence

4V/3 = 1 clock cycle = 1/3G secs
V = 1/4G...........(1)

Now largest stage that is stage 2 is split into equal size, so new pipeline is

(V)-->(2V/3)-->(2V/3)-->(V/2)

Now largest stage is V seconds
Hence,

In V seconds do 1 clock cycle
In 1 second do 1/V clock cycles
But V = 1/4G
So in 1 second do 4 Ghz. {ANS}
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