Skip to content
Related Articles

Related Articles

GATE | GATE-CS-2015 (Set 2) | Question 54

View Discussion
Improve Article
Save Article
  • Last Updated : 19 Nov, 2018
View Discussion
Improve Article
Save Article

Consider the sequence of machine instructions given below:

  MUL R5, R0, R1
  DIV R6, R2, R3
  ADD R7, R5, R6
  SUB R8, R7, R4 

In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the Result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is ___________
(A) 11
(B) 12
(C) 13
(D) 14

Answer: (C)


  1   2   3   4   5   6   7   8   9   10   11   12   13
  IF  OF  PO  PO  PO  WB
      IF  OF          PO  PO  PO  PO  PO   WB
          IF          OF                   PO   WB
              IF          OF                    PO   WB

Quiz of this Question

My Personal Notes arrow_drop_up
Recommended Articles
Page :

Start Your Coding Journey Now!