GATE | GATE-CS-2004 | Question 64
Directions for question 63 to 64: Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.
Instruction Operation Instruction Size(in words) MOV R1,5000; R1 ¬ Memory 2 MOV R2, (R1); R2 ¬ Memory[(R1)] 1 ADD R2, R3; R2 ¬ R2 + R3 1 MOV 6000, R2; Memory  ¬ R2 2 HALT Machine halts 1
Let the clock cycles required for various operations be as follows: Register to/ from memory transfer: 3 clock cycles ADD with both operands in register : 1 clock cycle Instruction fetch and decode : 2 clock cycles per word The total number of clock cycles required to execute the program is
Explanation: The clock cycles are per block; if an instruction size is 2 then it requires twice no. of clock cycles.
|Instruction no. size no. of clock cycles|
|1 2 3*1+2*2|
|2 1 1*3+2|
|3 1(add only) 2+3|
|4 2 3*1+2*2|
|5 1 2(fetch and decode)|
So answer is (B)
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