Skip to content
Related Articles

Related Articles

Improve Article

GATE | Gate IT 2005 | Question 44

  • Last Updated : 19 Nov, 2018

We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time How much time can be saved using design D2 over design D1 for executing 100 instructions?

 
(A) 214 nsec
(B) 202 nsec
(C) 86 nsec
(D) – 200 nsec


Answer: (B)

Explanation:
Total execution time = (k + n – 1) * maximum clock cycle
Where k = total number of stages and n = total number of instructions

For D1 :
k = 5 and n = 100
Maximum clock cycle = 4ns
Total execution time = (5 + 100 – 1) * 4 = 416

For D2 :
k = 8 and n = 100
Each clock cycle = 2ns
Total execution time = (8 + 100 – 1) * 2 = 214

Thus, time saved using D2 over D1 = 416 – 214 =202

 
Thus, option (B) is correct.

 
Please comment below if you find anything wrong in the above post.


Quiz of this Question

Attention reader! Don’t stop learning now.  Practice GATE exam well before the actual exam with the subject-wise and overall quizzes available in GATE Test Series Course.

Learn all GATE CS concepts with Free Live Classes on our youtube channel.

My Personal Notes arrow_drop_up
Recommended Articles
Page :