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UGC-NET | UGC NET CS 2016 July – II | Question 10

In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be _____ on the rising edge of the clock.

(A)



No change

(B)



Set

(C)

Reset

(D)

Toggle


Answer: (D)
Explanation:
Quiz of this Question
Please comment below if you find anything wrong in the above post

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