# Sequential circuits

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Question 1 |

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?

000 | |

001 | |

010 | |

011 |

**GATE CS 2011**

**Digital Logic & Number representation**

**Sequential circuits**

**Discuss it**

Question 1 Explanation:

P' = R
Q' = (P + R)'
R' = QR' Given that (P, Q, R) = (0, 1, 0), next state P', Q', R' = 0, 1, 1
-----------------------------------------------------------------------------------------------
D flip flop truth table

Initially (p,q,r) =(0,1,0)
D for p=R
D for q=NOT(p xor r)
D for r= (not)r.q
So Q(t+1) for(p,q,r)
p=>r=0 so p=0
q=> NOT(p xor r) => 1 so q=1
r=>(not)r.q => 1 so r=1
(p, q, r) = (0, 1, 1)

D | Q(t+1) |

0 | 0 |

1 | 1 |

**Alternative approach -**Truth table of a D Flip-Flop- By looking at the circuit diagram, it is clear that the boolean expressions of P, Q, and R are- Here the subscript t refers to the current clock cycle, and the subscript (t+1) refers to the next clock cycle. This explanation is provided by**Chirag Manwani**.Question 2 |

Consider the data given in previous question. If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR generated by the counter?

3 | |

4 | |

5 | |

6 |

**GATE CS 2011**

**Digital Logic & Number representation**

**Sequential circuits**

**Discuss it**

Question 2 Explanation:

There are four distinct states, 000 → 010 → 011 → 100 (→ 000) so the answer is B

Question 3 |

In the sequential circuit shown below,if the initial value of the output Q1Q0 is 00,what are the next four values of Q1Q0?

11, 10, 01, 00 | |

10, 11, 01, 00 | |

10, 00, 01, 11 | |

11, 10, 00, 01 |

**GATE CS 2010**

**Digital Logic & Number representation**

**Sequential circuits**

**Discuss it**

Question 3 Explanation:

We have t flip flop
Truth table of t flip flop

So q0 always inverted as t=1 always
So 1)q10=1
2)q0 =0
3)q0 =1
4)q0 =1
For q1 also t=1 always but clock is so we have to observe positive edge of clock I.e. when is q0 going from 0 -> 1
1)q1 =1
2)q1 =1
3)q1 =0
4)q1 =0
So final combination q0q1->(11,10,01,00) Ans (A)

t | q |

0 | q |

1 | q’ |

Question 4 |

The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”)
The counter is connected as follows:

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

0, 3, 4 | |

0, 3, 4, 5 | |

0, 1, 2, 3, 4 | |

0, 1, 2, 3, 4, 5 |

**Digital Logic & Number representation**

**GATE-CS-2007**

**Sequential circuits**

**Discuss it**

Question 4 Explanation:

Initially A1 A2 A3 A4 =0000
Clr=A1 and A3
So when A1 and A3 both are 1 it again goes to 0000
Hence 0000(init.) -> 0001(A1 and A3=0)->0010 (A1 and A3=0) -> 0011(A1 and A3=0) -> 0100 (

**A1 and A3=1**)[ clear condition satisfied] ->0000(init.) so it goes through 0->1->2->3->4 Ans is ( C) part.Question 5 |

You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°?

A | |

B | |

C | |

D |

**Digital Logic & Number representation**

**GATE-CS-2006**

**Sequential circuits**

**Discuss it**

Question 5 Explanation:

We assume the D flip-flop to be negative edge triggered.

In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’. Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output. So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

Therefore, (C) is the correct answer.

Please comment below if you find anything wrong in the above post.

In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’. Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output. So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

Therefore, (C) is the correct answer.

Please comment below if you find anything wrong in the above post.

Question 6 |

Let k = 2

^{n}. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2^{n}bit decoder. This circuit is equivalent to ak-bit binary up counter. | |

k-bit binary down counter. | |

k-bit ring counter. | |

k-bit Johnson counter. |

**Digital Logic & Number representation**

**GATE-CS-2014-(Set-2)**

**Sequential circuits**

**Discuss it**

Question 6 Explanation:

For output of a decoder , only single output will be ‘1’ and remaining will be ‘0’ at the same time. So high output will give the count of the ring counter. Hence Ans is ( C) part.

Question 7 |

The above sequential circuit is built using JK flip-flops is initialized with Q2Q1Q0 = 000. The state sequence for this circuit for the next 3 clock cycle is

001, 010, 011 | |

111, 110, 101 | |

100, 110, 111 | |

100, 011, 001 |

**Digital Logic & Number representation**

**GATE-CS-2014-(Set-3)**

**Sequential circuits**

**Discuss it**

Question 7 Explanation:

JK ff truth table---

Initially Q2Q1Q0=000
Present state FF input Next state

So ans is ( C) part.

j | k | Q |

0 | 0 | Q0 |

1 | 0 | 1 |

0 | 1 | 0 |

1 | 1 | Q0’ |

Q2 | Q1 | Q0 | J2 | K2 | J1 | K1 | J0 | K0 | Q2 | Q1 | Q0 |

0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 |

1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 |

1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |

Question 8 |

Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flipflops are initialized to zeroes (cleared).
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:

000 | |

001 | |

010 | |

101 |

**Digital Logic & Number representation**

**GATE-CS-2006**

**Sequential circuits**

**Discuss it**

Question 8 Explanation:

The D flipflops are initialized to zeroes. This implies q0 = 0, q1 = 0 and q2 = 0 initially.

**Clock cycle 1 :**q0 = data = 1 , q1 = q0

_{before}XOR q2

_{before}= 0 XOR 0 = 0 , q2 = q1

_{before}= 0

**Clock cycle 2 :**q0 = data = 0 , q1 = q0

_{before}XOR q2

_{before}= 1 XOR 0 = 1 , q2 = q1

_{before}= 0

**Clock cycle 3 :**q0 = data = 0 , q1 = q0

_{before}XOR q2

_{before}= 0 XOR 0 = 0 , q2 = q1

_{before}= 1

**Clock cycle 4 :**q0 = data = 1 , q1 = q0

_{before}XOR q2

_{before}= 0 XOR 1 = 1 , q2 = q1

_{before}= 0

**Clock cycle 5 :**q0 = data = 1 , q1 = q0

_{before}XOR q2

_{before}= 1 XOR 0 = 1 , q2 = q1

_{before}= 1

**Clock cycle 6 :**q0 = data = 0 , q1 = q0

_{before}XOR q2

_{before}= 1 XOR 1 = 0 , q2 = q1

_{before}= 1

**Clock cycle 7 :**q0 = data = 0 , q1 = q0

_{before}XOR q2

_{before}= 0 XOR 1 = 1 , q2 = q1

_{before}= 0

**Clock cycle 8 :**q0 = data = 0 , q1 = q0

_{before}XOR q2

_{before}= 0 XOR 0 = 0 , q2 = q1

_{before}= 1

**Clock cycle 9 :**q0 = data = 0 , q1 = q0

_{before}XOR q2

_{before}= 0 XOR 1 = 1 , q2 = q1

_{before}= 0

Thus, option (C) is correct.

Please comment below if you find anything wrong in the above post.

Question 9 |

Consider the following circuit involving a positive edge triggered D FF.
Consider the following timing diagram. Let Ai represent the logic level on the line A in the i-th clock period.
Let A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is

A0 Al A1' A3 A4 | |

A0 Al A2' A3 A4 | |

Al A2 A2' A3 A4 | |

Al A2' A3 A4 A5' |

**Digital Logic & Number representation**

**GATE-CS-2005**

**Sequential circuits**

**Discuss it**

Question 9 Explanation:

The Flip Flop used here is a Positive edge triggered D Flip Flop, which means that only at the "

**rising edge of the clock**" flip flop will capture the input provided at D and accordingly give the output at Q. And at other times of the clock the output doesn't change. The output of D flip flop is same as input, i.e. Y=Q=D ( at the rising edge ). Now, in the question above, 5 clock periods are given, and we have to find the output Q or Y in those clock periods. First, let's derive the boolean expression for the Logic gate. which is :**D = AX****+ X' Q'**Now,**In the 1st clock period**, (i.e. when t = 0 to 1 ) here the clock has rising edge at t= 0, hence at this moment only, D flip flop will change its state. In the 1st clock, X = 1, So, D = A. Now A logic line may have different levels at different clock periods, i.e. may be high or low, therefore we have to answer with respect to the ith clock period where Ai is the logic level ( high or low ) of logic line A in the ith clock. So in the 1st clock period, A logic value should be A1 ( i.e. value of A in 1st clock period), but due to the**delay provided by the Logic Gates ( Propagation Delay)**the value of A used by Flip Flop is previous value of A only, i.e.it will capture the value of D resulted by using the logic line A in the 0th clock period, which is A0. Same happens with the value of X, i.e. instead of Xi, previous value of X is used in the in the ith clock period, which is Xi-1. Now, In the 1st clock period value of X is same as in the 0th clock, i.e. logic 1. So, X = 1 ,and A = A0, therefore, D = A0, and hence Q =**Y = A0**Similarly we have to do for other clock periods, i.e. instead of taking Ai and Xi, Ai-1 and Xi-1 need to be taken for getting the output in the ith clock period.**In the 2nd clock period**, (i.e. when t = 1 to 2 ) X = 1 ( value in the previous clock), So, D = A1 ( value of A in the previous clock) , therefore Q =**Y = A1****In the 3rd clock period**, (i.e. when t = 2 to 3 ) X = 0 ( value in the previous clock,see the timing diagram), So, D = Q' = A1' , therefore Q =**Y = A1'**( because of the feedback line )**In the 4th clock period**, (i.e. when t = 3 to 4 ) X = 1 ( value in the previous clock, ), So, D = A3 , therefore Q =**Y = A3****In the 5th clock period**, (i.e. when t = 4 to 5 ) X = 1 ( value in the previous clock ), so, D = A4 , therefore Q =**Y = A4**Hence the output sequence is :**A0 A1 A1' A3 A4**Question 10 |

Consider the following circuit
The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial state be 00. The state transition sequence is:

A) B) C) D)

A | |

B | |

C | |

D |

**Digital Logic & Number representation**

**GATE-CS-2005**

**Sequential circuits**

**Discuss it**

Question 10 Explanation:

Q

_{0}will toggle in every cycle because Q_{0}' (Q_{0}complement) is fed as input to the D_{0}flip flop. For the D_{1}flip flop, D_{1}= Q_{0}⊕ Q_{1}' , i.e., Q_{0}XOR Q_{1}'. So, the bit pattern Q_{0}Q_{1}will be :QThus, the transition sequence will be_{0}Q_{1}0 0 1 1 0 1 1 0 0 0 . . . . . .

**So, D would be the correct choice.**Please comment below if you find anything wrong in the above post.
There are 46 questions to complete.