GATE | GATE CS Mock 2018 | Set 2 | Question 57

The next state table of a 2 bit saturating up-counter is given below. The counter is built as synchronous sequential circuit using D flip-flops. The value for D₁ and D₂ are

(A)

D₁ = Q₀ + Q₁ D₂ = Q\’₀ + Q₁

(B)

D₁ = Q\’₁Q₀ D₂ = Q\’₁ + Q\’₀

(C)

D₁ = Q\’₀ + Q₁ D₂ = Q₀ + Q₁

(D)

None of these

Answer: (A)
Explanation:

Since D = Q, so; Using above excitation table, D₁ = Q₀ + Q₁ D₂ = Q\’₀ + Q₁ Option (A) is correct.

Quiz of this Question
Please comment below if you find anything wrong in the above post

Article Tags :

GATE

Recommended Articles

1. GATE | GATE CS Mock 2018 | Set 2 | Question 23

2. GATE | GATE CS Mock 2018 | Set 2 | Question 24

3. GATE | GATE CS Mock 2018 | Set 2 | Question 25

4. GATE | GATE CS Mock 2018 | Set 2 | Question 26

5. GATE | GATE CS Mock 2018 | Set 2 | Question 27

6. GATE | GATE CS Mock 2018 | Set 2 | Question 28

7. GATE | GATE CS Mock 2018 | Set 2 | Question 29

8. GATE | GATE CS Mock 2018 | Set 2 | Question 30

9. GATE | GATE CS Mock 2018 | Set 2 | Question 31

10. GATE | GATE CS Mock 2018 | Set 2 | Question 32

11. GATE | GATE CS Mock 2018 | Set 2 | Question 33

12. GATE | GATE CS Mock 2018 | Set 2 | Question 34

13. GATE | GATE CS Mock 2018 | Set 2 | Question 35

14. GATE | GATE CS Mock 2018 | Set 2 | Question 36

15. GATE | GATE CS Mock 2018 | Set 2 | Question 37

16. GATE | GATE CS Mock 2018 | Set 2 | Question 38

17. GATE | GATE CS Mock 2018 | Set 2 | Question 39

18. GATE | GATE CS Mock 2018 | Set 2 | Question 40

19. GATE | GATE CS Mock 2018 | Set 2 | Question 41

20. GATE | GATE CS Mock 2018 | Set 2 | Question 42

21. GATE | GATE CS Mock 2018 | Set 2 | Question 22

22. GATE | GATE CS Mock 2018 | Set 2 | Question 1

23. GATE | GATE CS Mock 2018 | Set 2 | Question 2

24. GATE | GATE CS Mock 2018 | Set 2 | Question 3

25. GATE | GATE CS Mock 2018 | Set 2 | Question 4