Pipelining and Addressing modes

Question 31

Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non­ pipelined but identical CPU, we can say that

• T1 <= T2
• T1 >= T2
• T1 < T2
• T1 is T2 plus the time taken for one instruction fetch cycle

Question 32

The most appropriate matching for the following pairs

X: Indirect addressing            1 : Loops

Y: Immediate addressing           2 : Pointers

Z: Auto decrement addressing      3: Constants

is

• X-3, Y-2, Z-1
• X-I, Y-3, Z-2
• X-2, Y-3, Z-1
• X-3, Y-l, Z-2

Question 33

For computers based on three-address instruction formats, each address field can be used to specify which of the following:

S1: A memory operand
S2: A processor register
S3: An implied accumulator register

• Either S1 or S2
• Either S2 or S3
• Only S2 and S3
• All of S1, S2 and S3

Question 34

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is __________.

• 3.2
• 3.0
• 2.2
• 2.0

Question 35

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)₁₆ and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)₁₆. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:

   • Store the current value of PC in the stack.
   • Store the value of PSW register in the stack.
   • Load the starting address of the subroutine in PC. 

The content of PC just before the fetch of a CALL instruction is (5FA0)₁₆. After execution of the CALL instruction, the value of the stack pointer is
A.(016A)₁₆
B.(016C)₁₆
C.(0170)₁₆
D.(0172)₁₆

• A
• B
• C
• D

Question 36

Consider the sequence of machine instructions given below:

  MUL R5, R0, R1
  DIV R6, R2, R3
  ADD R7, R5, R6
  SUB R8, R7, R4 

In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the Result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is ___________

• 11

• 12

• 13

• 14

Question 37

Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format.

    OP Ri, Rj, Rk 

where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.

   I1 : ADD R1, R2, R3
   I2 : MUL R7, R1, R3
   I3 : SUB R4, R1, R5
   I4 : ADD R3, R2, R4
   I5 : MUL R7, R8, R9 

Consider the following three statements:

S1: There is an anti-dependence between instructions I2 and I5.
S2: There is an anti-dependence between instructions I2 and I4.
S3: Within an instruction pipeline an anti-dependence always 
    creates one or more stalls. 

Which one of above statements is/are correct?

• Only S1 is true
• Only S2 is true
• Only S1 and S2 are true
• Only S2 and S3 are true

Question 38

Consider the following reservation table for a pipeline having three stages S1, S2 and S3.

     Time -->
-----------------------------
      1    2   3    4     5
-----------------------------
S1  | X  |   |   |    |  X |    
S2  |    | X |   | X  |    |
S3  |    |   | X |    |    |

The minimum average latency (MAL) is __________

• 3
• 2
• 1
• 4

Question 39

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of cycles needed to execute the following loop?

for (i = 1; i < = 1000; i++) 
    {I1, I2, I3, I4}

• 11 ns
• 12 ns
• 13 ns
• 28 ns

Question 40

In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 20% and the speed of a fixed point unit has been increased by 10%. What is the overall speedup achieved if the ratio of the number of floating point operations to the number of fixed point operations is 2:3 and the floating point operation used to take twice the time taken by the fixed point operation in the original design?

• 1.155
• 1.185
• 1.255
• 1.285