Pipelining and Addressing modes

Question 11

Which of the following is/are true of the auto-increment addressing mode?

I.  It is useful in creating self-relocating code.
II. If it is included in an Instruction Set Architecture, 
    then an additional ALU is required for effective address 
    calculation.
III.The amount of increment depends on the size of the data
     item accessed.

• I only
• II only
• III Only
• II and III only

Question 12

Which of the following must be true for the RFE (Return from Exception) instruction on a general purpose processor?

I.   It must be a trap instruction
II.  It must be a privileged instruction
III. An exception cannot be allowed to occur during 
     execution of an RFE instruction 

• I only
• II only
• I and II only
• I, II and III only

Question 13

Which of the following are NOT true in a pipelined processor?

I.  Bypassing can handle all RAW hazards.
II. Register renaming can eliminate all register 
    carried WAR hazards.
III. Control hazard penalties can be eliminated by 
     dynamic branch prediction.

• I and II only
• I and III only
• II and III only
• I, II and III

Question 14

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is

• before effective address calculation has started

• during effective address calculation

• after effective address calculation has completed

• after data cache lookup has completed

Question 15

Consider a pipelined processor with the following four stages:

IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage dependson the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

ADD R2, R1, R0       R2 <- R0 + R1
MUL R4, R3, R2       R4 <- R3 * R2
SUB R6, R5, R4       R6 <- R5 - R4  

• 7
• 8
• 10
• 14

Question 16

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:

• 10
• 11
• 20
• 21

Question 17

Consider the data given in above question. Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

• 100
• 101
• 102
• 110

Question 18

Consider the data given in above questions. Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?

• 1005
• 1020
• 1024
• 1040

Question 19

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________.

• 16383
• 16338
• 16388
• 16484

Question 20

Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is

• 4
• 8
• 6
• 7