Pipelining and Addressing modes

Question 41

We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time How much time can be saved using design D2 over design D1 for executing 100 instructions?  

• 214 nsec
• 202 nsec
• 86 nsec
• - 200 nsec

Question 42

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is _______ percent. [This Question was originally a Fill-in-the-Blanks question]

• 33 or 34
• 30 or 31
• 38 or 39
• 100

Question 43

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is ____________ [This Question was originally a Fill-in-the-blanks Question]

• 16
• 8
• 4
• 32

Question 44

Suppose the functions F and G can be computed in 5 and 3 nanoseconds by functional units U_F and U_G, respectively. Given two instances of U_F and two instances of U_G, it is required to implement the computation F(G(Xi)) for 1 <= i <= 10. ignoring all other delays, the minimum time required to complete this computation is ________________ nanoseconds [Note that this is originally a Fill-in-the-Blanks Question]

• 28
• 20
• 18
• 30

Question 45

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is ____________ [Note that this was originally a Fill-in-the-Blanks question]

• 100
• 200
• 400
• 500

Question 46

Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies v1, v2, and v3 such that v1 = 3v2/4 = 2v3. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is _________ GHz, ignoring delays in the pipeline registers

• 2
• 4
• 8
• 16

Question 47

Which of the following statements about relative addressing mode is FALSE?

• It enables reduced instruction size

• It allows indexing of array elements with same instruction

• It enables easy relocation of data

• It enables faster address calculations than absolute addressing

Question 48

A processor takes 12 cycles to complete an instruction I. The corresponding pipelined processor uses 6 stages with the execution times of 3, 2, 5, 4, 6 and 2 cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed?

• 1.83
• 2
• 3
• 6

Question 49

A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2\'s complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:

• 1, 1, 0
• 1, 0, 0
• 0, 1, 0
• 1, 0, 1

Question 50

Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)− is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination ← source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.

• ADD (X)−, (X)
• ADD (X), (X)−
• ADD −(X), (X)+
• ADD −(X), (X)+