Cache and main memory

Question 51

A two way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The physical address space is 4 GB. The number of bits in the TAG, SET fields are

• 20, 7
• 19, 8
• 20, 8
• 21, 9

Question 52

A CPU has a 32 KB direct mapped cache with 128 byte block size. Suppose A is a 2 dimensional array of size 512×512 with elements that occupy 8 bytes each. Consider the code segment

for (i =0; i < 512; i++) {
  for (j =0; j < 512; j++) {
    x += A[i][j];
  }
} 

Assuming that array is stored in order A[0][0], A[0][1], A[0][2]……, the number of cache misses is

• 16384
• 512
• 2048
• 1024

Question 53

In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

• Smaller block size incurs lower cache miss penalty
• Smaller block size implies better spatial locality
• Smaller block size implies smaller cache tag
• Smaller block size implies lower cache hit time

Question 54

The most appropriate matching for the following pairs :

X : Indirect Addressing          1. Loop
Y : Immediate Addressing         2. Pointers
Z : Auto Decrement Addressing    3. Constants

• X − 3, Y − 2, Z −1
• X − 2, Y − 3, Z −1
• X − 3, Y −1, Z − 2
• X − 2, Y −1, Z − 3

Question 55

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is

• 3.2
• 3.0
• 2.2
• 2.0

Question 56

Suppose you want to build a memory with 4 byte words with a capacity of 2²¹bits. What is type of decoder required if the memory is built using 2K x 8 RAM chips?

• 5 to 32
• 6 to 64
• 4 to 64
• 7 to 128

Question 57

A processor takes 12 cycles to complete an instruction I. The corresponding pipelined processor uses 6 stages with the execution times of 3, 2, 5, 4, 6 and 2 cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed?

• 1.83
• 2
• 3
• 6

Question 58

Number of chips (128 x 8 RAM) needed to provide a memory capacity of 2048 bytes

• 2
• 4
• 8
• 16

Question 59

A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is ________ . Note - This question was Numerical Type.

• 13.5
• 15.5
• 23.5
• 15.3

Question 60

A computer system with a word length of 32 bits has a 16 MB byte- addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.

A1 = 0x42C8A4,
A2 = 0x546888,
A3 = 0x6A289C,
A4 = 0x5E4880 

Which one of the following is TRUE ?

• A1 and A4 are mapped to different cache sets.
• A2 and A3 are mapped to the same cache set.
• A3 and A4 are mapped to the same cache set.
• A1 and A3 are mapped to the same cache set.