Cache and main memory

Question 21

In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

• A smaller block size implies better spatial locality
• A smaller block size implies a smaller cache tag and hence lower cache tag overhead
• A smaller block size implies a larger cache tag and hence lower cache hit time
• A smaller block size incurs a lower cache miss penalty

Question 22

If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?

• Width of tag comparator

• Width of set index decoder

• Width of way selection multiplexer

• Width of processor to main memory data bus

Question 23

A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c − byte chunks are mapped on consecutive banks with wrap-around. All the k banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes. k/2 ns The latency of one bank access is 80 ns. If c = 2 and k = 24, the latency of retrieving a cache block starting at address zero from main memory is:

• 92 ns

• 104 ns

• 172 ns

• 184 ns

Question 24

Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative organization is h1 while that of the direct mapped one is h2. The value of h1 is:

• 2.4 ns

• 2.3 ns

• 1.8 ns

• 1.7 ns

Question 25

Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative organization is h1 while that of the direct mapped one is h2. The value of h1 is:

• 2.4 ns

• 2.3

• 1.8

• 1.7

Question 26

A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a twodimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2. P1:

C

 
for (i=0; i<512; i++) {
   for (j=0; j<512; j++) {
      x += A[i][j];
   }
} 

P2:

C

 
for (i=0; i<512; i++) {
   for (j=0; j<512; j++) {
      x += A[j][i];
   }
}

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 . The value of M1 is:

• 0
• 2048
• 16384
• 262144

Question 27

A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a twodimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2. P1:

C

 
for (i=0; i<512; i++) {
   for (j=0; j<512; j++) {
      x += A[i][j];
   }
} 

P2:

C

 
for (i=0; i<512; i++) {
   for (j=0; j<512; j++) {
      x += A[j][i];
   }
}

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 . The value of the ratio M1/M2 is:

• 0
• 1/16
• 1/8
• 16

Question 28

Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively

• 10, 17
• 10, 22
• 15, 17
• 5, 17

Question 29

Consider a machine with byte addressable memory of 2^32 bytes divided into blocks of size 32 bytes. Assume a 2-set associative cache having 512 cache lines is used with this machine. The size of tag field in bits is _____

• 18
• 16
• 19
• 21

Question 30

More than one word are put in one cache block to

• exploit the temporal locality of reference in a program
• exploit the spatial locality of reference in a program
• reduce the miss penalty
• none of the above