Cache and main memory

Question 31

Where does the swap space reside?

• RAM
• Disk
• ROM
• On-chip cache

Question 32

Assume that for a certain processor, a read request takes 50 nanoseconds on a cache miss and 5 nanoseconds on a cache hit. Suppose while running a program, it was observed that 80% of the processor’s read requests result in a cache hit. The average read access time in nanoseconds is____________.

• 10
• 12
• 13
• 14

Question 33

Consider a machine with a byte addressable main memory of 2²⁰ bytes, block size of 16 bytes and a direct mapped cache having 2¹² cache lines. Let the addresses of two consecutive bytes in main memory be (E201F)₁₆ and (E2020)₁₆. What are the tag and cache line address (in hex) for main memory address (E201F)₁₆?

• E, 201
• F, 201
• E, E20
• 2, 01F

Question 34

Consider a system with 2 level caches. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?

• 13.0 ns
• 12.8 ns
• 12.6 ns
• 12.4 ns

Question 35

A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each refresh takes 100 nsec. What percentage of the memory cycle time is used for refreshing?

• 10
• 6.4
• 1
• .64

Question 36

A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at ____ least bits.   Note : This question was asked as Numerical Answer Type.

• 16
• 31
• 32
• None

Question 37

The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is ____________ bits

• 24
• 20
• 30
• 40

Question 38

A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is 1 ms and to read a block from the disk is 10 ms. Assume that the cost of checking whether a block exists in the cache is negligible. Available cache sizes are in multiples of 10 MB. The smallest cache size required to ensure an average read latency of less than 6 ms is _______ MB.

• 10
• 20
• 30
• 40

Question 39

A cache line is 64 bytes. The main memory has latency 32ns and bandwidth 1G.Bytes/s. The time required to fetch the entire cache line from the main memory is

• 32 ns
• 64 ns
• 96 ns
• 128 ns

Question 40

A computer system has a level-1 instruction cache (1-cache), a level-1 data cache (D-cache) and a level-2 cache (L2-cache) with the following specifications:

The length of the physical address of a word in the main memory is 30 bits. The capacity of the tag memory in the I-cache, D-cache and L2-cache is, respectively,

• 1 K x 18-bit, 1 K x 19-bit, 4 K x 16-bit
• 1 K x 16-bit, 1 K x 19-bit, 4 K x 18-bit
• 1 K x 16-bit, 512 x 18-bit, 1 K x 16-bit
• 1 K x 18-bit, 512 x 18-bit, 1 K x 18-bit