Cache and main memory

Question 41

Consider a computer with a 4-ways set-associative mapped cache of the following characteristics: a total of 1 MB of main memory, a word size of 1 byte, a block size of 128 words and a cache size of 8 KB. The number of bits in the TAG, SET and WORD fields, respectively are:

• 7, 6, 7
• 8, 5, 7
• 8, 6, 6
• 9, 4, 7

Question 42

Consider a computer with a 4-ways set-associative mapped cache of the following character­istics: a total of 1 MB of main memory, a word size of 1 byte, a block size of 128 words and a cache size of 8 KB. While accessing the memory location 0C795H by the CPU, the contents of the TAG field of the corresponding cache line is

• 000011000
• 110001111
• 00011000
• 110010101

Question 43

The main memory of a computer has 2 cm blocks while the cache has 2c blocks. If the cache uses the set associative mapping scheme with 2 blocks per set, then the block k of main memory maps to the set:

• (k mod m) of the cache
• (k mod c) of the cache
• (k mod 2c) of the cache
• (k mod 2cm) of the cache

Question 44

[5 Marks question] For a set-associative Cache Organization, the parameters are as follows:

tc - Cache access tine
tm - Main memory access time
l - number of sets
b - block size
k x b - set size

Calculate the hit ratio for a loop executed 100 times where the size of the loop is n X b and n= k X m is a non-zero integer and 1 < m ≤ l. Given the value of the hit ratio for l = 1.

Question 45

A computer system has a three level memory hierarchy, with access time and hit ratios as shown below:         a) What should be the minimum sizes of level 1 and 2 memories to achieve an average access time of less than 100 nsec? b) What is the average access time achieved using the chosen sizes of level 1 and level 2 memories?

Question 46

Consider an array A[999] & each element occupies 4 word. A 32 word cache is used and divided into 16 word blocks. What is the miss ratio for the following statement. Assume one block is read into cache in case of miss:

for(i=0; i < 1000; i++)
  A[i] = A[i] + 99

• 0.50
• 0.75
• 0.875
• 0.125

Question 47

A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as a 16-way set-associative cache, the length of the TAG field is 10 bits. If the cache unit is now designed as direct mapped cache, the length of the TAG field is ______ bits.

• 6
• 14
• 16
• None of these

Question 48

The read access times and the hit ratios for different caches in a memory hierarchy are as given below: The read access time of main memory in 90 nanoseconds. Assume that the caches use the referred-word-first read policy and the writeback policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the caches. In execution of a program, 60% of memory reads are for instruction fetch and 40% are for memory operand fetch. What is total value of average data fetch time multiplied by average instruction fetch time?

• 4.72
• 16.89
• 9.1
• 19.98

Question 49

Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocks and the request for memory blocks is in the following order: 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155. Find the total number of hit(s) occurred in the cache using least recently used (LRU) page replacement algorithm?

• 0
• 1
• 2
• 3

Question 50

The size of the physical address space of a processor is 2^P bytes. The word length is 2^W bytes. The capacity of cache memory is 2^N bytes. The size of each cache block is 2^M words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is

• P − N − log₂K
• P − N + log₂K
• P − N − M − W − log₂K
• P − N − M − W + log₂K