Cache and main memory

Question 11

Consider the data from above question. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?

• 222 nanoseconds
• 888 nanoseconds
• 902 nanoseconds
• 968 nanoseconds

Question 12

How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?

• 8
• 32
• 64
• 128

Question 13

Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocks and the request for memory blocks is in the following order: 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155. Which one of the following memory block will NOT be in cache if LRU replacement policy is used?

• 3
• 8
• 129
• 216

Question 14

For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary?

I. L1 must be a write-through cache
II. L2 must be a write-through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache 

• IV only
• I and IV only
• I, III and IV only
• I, II, III and IV

Question 15

Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache is managed using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins as follows: 

C

double ARR[1024][1024];
int i, j;
// Initialize array ARR to 0.0
for(i = 0; i < 1024; i++)
    for(j = 0; j < 1024; j++)
        ARR[i][j] = 0.0;

The size of double is 8 Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR. The total size of the tags in the cache directory is

• 32 Kbits

• 34 Kbits

• 64 Kbits

• 68 Kbits

Question 16

The cache hit ratio for this initialization loop is

• 0%
• 25%
• 50%
• 75%

Question 17

Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields arerespectively:

• 9,6,5

• 7, 7, 6

• 7, 5, 8

• 9, 5, 6

Question 18

Consider a machine with a byte addressable main memory of 2¹⁶ bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A 50 × 50 two-dimensional array of bytes is stored in the main memory starting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses. How many data cache misses will occur in total?

• 40
• 50
• 56
• 59

Question 19

Consider the data given in above question. Which of the following lines of the data cache will be replaced by new blocks in accessing the array for the second time?

• line 4 to line 11
• line 4 to line 12
• line 0 to line 7
• line 0 to line 8

Question 20

A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG field is _____

• 5

• 15

• 20

• 25