PowerPC Architecture

PowerPC Architecture are microprocessor for personal computers. PowerPC is a RISC (Reduced Instruction Set Computer) architecture which are very powerful and low-cost microprocessors. RISC architecture tries to keep the processor as busy as possible. 

Design features of PowerPC are as follows: 

• Broad range implementation
• Simple processor design
• Superscalar architecture
• Multiprocessor features
• 64-bit architecture
• Support for operation in both big-endian and little-endian mode. PowerPC can switch from one mode to another at run time.
• Separate set of Floating Point Registers (FPRs) for floating-point instructions

PowerPC machine Architecture:

• Memory:
  Memory consists of 8-bit bytes. Two consecutive bytes form a halfword, four bytes form a word, eight bytes form a doubleword, sixteen bytes form a quadword. PowerPC programs can be written using a Virtual Address Space (2⁶⁴ bytes). Address space are divided into fixed-length segments which are further divided into pages. 
• Registers:
  There are 32 general-purpose registers (GPR) from GPR0 to GPR31. Length of each register is 64-bit. The general purpose register are used to store and manipulate data and addresses. As PowerPC machine support floating point data format so it have Floating-point unit (FPU) for computation. 
  Some of the register’s supported by PowerPC architecture are: 

Register                   Operations
Link Register(LR)          Contain address to return at 
                           the end of the function call

Condition Register         Signify the result of an
(CR)                       instruction

Count Register             For Loop count
(CTR) 

• Data Formats:
  • Integers are stored as 8-, 16-, 32-, or 64-bit Binary numbers.
  • Characters are represented using 8-bit ASCII codes.
  • Floating points are represented using two different floating-point formats namely single-precision format and double-precision format.
• Instruction Formats:
  PowerPC support seven basic instruction formats. All of these instruction formats are 32-bits long. PowerPC architecture instruction format have more variety and complexity as compared to other RISC systems such as SPARC. Bit numbering for PowerPC is the opposite of most other definitions: 

bit 0 is the most significant bit, and 
bit 31 is the least significant bit 

Instructions are first decoded by the upper 6 bits in a field, called the primary opcode. The remaining 26 bits contain fields for operand specifiers, immediate operands, and extended opcodes, and these may be reserved bits or fields. 

• Addressing Mode:
  Load and store operations use one of the following three addressing mode depending upon the operand value: 

Mode                      Target address(TA) calculation
Register indirect         TA=(register)

Register indirect         TA=(register-1) + (register-2)
with index

Register indirect         TA=(register) + displacement
with immediate
index 

Branch instructions use one of the following three addressing modes: 

Mode                      Target address(TA) calculation
Absolute                  TA=actual address

Relative                  TA=current instruction address + displacement

Link Register             TA=(LR) 

Count Register            TA=(CR) 

• Instruction Set:
  PowerPC architecture is more complex than the other RISC systems. Thus PowerPC architecture has approximately 200 machine instructions. This architecture follows the pipeline execution of instructions which means while one instruction is executed next one is being fetched from memory and decoded. 
• Input and Output:
  PowerPC architecture follows two different methods for performing I/O operations. In one approach Virtual address space is used while in the other approach I/O is performed using Virtual memory management.